Commit 88d5cb25 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/display: drop DCN support for aarch64 



From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.

So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."

Disable support until the code can be properly refactored to support this
properly on aarch64.

Acked-by: default avatarWill Deacon <will@kernel.org>
Reported-by: default avatarArd Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3e7bc83e

drivers/gpu/drm/amd/display/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ config DRM_AMD_DC 
	bool "AMD DC - Enable new display engine"

	default y

	select SND_HDA_COMPONENT if SND_HDA_CORE

	select DRM_AMD_DC_DCN if (X86 || PPC64 || (ARM64 && KERNEL_MODE_NEON)) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)

	select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)

	help

	  Choose this option if you want to use the new display engine

	  support for AMDGPU. This adds required support for Vega and

drivers/gpu/drm/amd/display/dc/calcs/Makefile

+0 −4
Original line number Diff line number Diff line
@@ -33,10 +33,6 @@ ifdef CONFIG_PPC64 
calcs_ccflags := -mhard-float -maltivec

endif



ifdef CONFIG_ARM64

calcs_rcflags := -mgeneral-regs-only

endif



ifdef CONFIG_CC_IS_GCC

ifeq ($(call cc-ifversion, -lt, 0701, y), y)

IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

+0 −21
Original line number Diff line number Diff line
@@ -104,13 +104,6 @@ ifdef CONFIG_PPC64 
CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)

endif



# prevent build errors:

# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types

# this file is unused on arm64, just like on ppc64

ifdef CONFIG_ARM64

CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := -mgeneral-regs-only

endif



AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
@@ -125,13 +118,6 @@ ifdef CONFIG_PPC64 
CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)

endif



# prevent build errors:

# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types

# this file is unused on arm64, just like on ppc64

ifdef CONFIG_ARM64

CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := -mgeneral-regs-only

endif



AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
@@ -146,13 +132,6 @@ ifdef CONFIG_PPC64 
CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)

endif



# prevent build errors:

# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types

# this file is unused on arm64, just like on ppc64

ifdef CONFIG_ARM64

CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := -mgeneral-regs-only

endif



AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

+0 −7
Original line number Diff line number Diff line
@@ -31,11 +31,4 @@ DCN10 = dcn10_init.o dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ 


AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))



# fix:

# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types

# aarch64 does not support soft-float, so use hard-float and handle this in code

ifdef CONFIG_ARM64

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn10/dcn10_resource.o := -mgeneral-regs-only

endif



AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+0 −7
Original line number Diff line number Diff line
@@ -1534,15 +1534,8 @@ static bool dcn10_resource_construct( 
	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));

	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));



#if defined(CONFIG_ARM64)

	/* Aarch64 does not support -msoft-float/-mfloat-abi=soft */

	DC_FP_START();

	dcn10_resource_construct_fp(dc);

	DC_FP_END();

#else

	/* Other architectures we build for build this with soft-float */

	dcn10_resource_construct_fp(dc);

#endif



	pool->base.pp_smu = dcn10_pp_smu_create(ctx);