Commit 8882f90a authored by Stanley.Yang's avatar Stanley.Yang Committed by Alex Deucher
Browse files

drm/amdgpu: add new query interface for umc block v2 



add message smu to query error information

v2:
    rename message_smu to ecc_info

Signed-off-by: default avatarStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6edc8f8a

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

+16 −0
Original line number Diff line number Diff line
@@ -319,6 +319,19 @@ struct ras_common_if { 
	char name[32];

};



#define MAX_UMC_CHANNEL_NUM 32



struct ecc_info_per_ch {

	uint16_t ce_count_lo_chip;

	uint16_t ce_count_hi_chip;

	uint64_t mca_umc_status;

	uint64_t mca_umc_addr;

};



struct umc_ecc_info {

	struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];

};



struct amdgpu_ras {

	/* ras infrastructure */

	/* for ras itself. */
@@ -358,6 +371,9 @@ struct amdgpu_ras { 
	struct delayed_work ras_counte_delay_work;

	atomic_t ras_ue_count;

	atomic_t ras_ce_count;



	/* record umc error info queried from smu */

	struct umc_ecc_info umc_ecc;

};



struct ras_fs_data {

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

+4 −0
Original line number Diff line number Diff line
@@ -49,6 +49,10 @@ struct amdgpu_umc_ras_funcs { 
	void (*query_ras_error_address)(struct amdgpu_device *adev,

					void *ras_error_status);

	bool (*query_ras_poison_mode)(struct amdgpu_device *adev);

	void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,

				      void *ras_error_status);

	void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,

					void *ras_error_status);

};



struct amdgpu_umc_funcs {

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

+161 −0
Original line number Diff line number Diff line
@@ -50,6 +50,165 @@ static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev, 
	return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst;

}



static inline uint32_t get_umc_v6_7_channel_index(struct amdgpu_device *adev,

					      uint32_t umc_inst,

					      uint32_t ch_inst)

{

	return adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];

}



static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,

						   uint32_t channel_index,

						   unsigned long *error_count)

{

	uint32_t ecc_err_cnt;

	uint64_t mc_umc_status;

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);



	/*

	 * select the lower chip and check the error count

	 * skip add error count, calc error counter only from mca_umc_status

	 */

	ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_lo_chip;



	/*

	 * select the higher chip and check the err counter

	 * skip add error count, calc error counter only from mca_umc_status

	 */

	ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_hi_chip;



	/* check for SRAM correctable error

	  MCUMC_STATUS is a 64 bit register */

	mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)

		*error_count += 1;

}



static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev,

						      uint32_t channel_index,

						      unsigned long *error_count)

{

	uint64_t mc_umc_status;

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);



	/* check the MCUMC_STATUS */

	mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;

	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))

		*error_count += 1;

}



static void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,

					   void *ras_error_status)

{

	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;



	uint32_t umc_inst        = 0;

	uint32_t ch_inst         = 0;

	uint32_t umc_reg_offset  = 0;

	uint32_t channel_index	 = 0;



	/*TODO: driver needs to toggle DF Cstate to ensure

	 * safe access of UMC registers. Will add the protection */

	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {

		umc_reg_offset = get_umc_v6_7_reg_offset(adev,

							 umc_inst,

							 ch_inst);

		channel_index = get_umc_v6_7_channel_index(adev,

							 umc_inst,

							 ch_inst);

		umc_v6_7_ecc_info_query_correctable_error_count(adev,

						      channel_index,

						      &(err_data->ce_count));

		umc_v6_7_ecc_info_querry_uncorrectable_error_count(adev,

							  channel_index,

							  &(err_data->ue_count));

	}

}



static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,

					 struct ras_err_data *err_data,

					 uint32_t umc_reg_offset,

					 uint32_t ch_inst,

					 uint32_t umc_inst)

{

	uint64_t mc_umc_status, err_addr, retired_page;

	struct eeprom_table_record *err_rec;

	uint32_t channel_index;

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);



	channel_index =

		adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];



	mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;



	if (mc_umc_status == 0)

		return;



	if (!err_data->err_addr)

		return;



	err_rec = &err_data->err_addr[err_data->err_addr_cnt];



	/* calculate error address if ue/ce error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {



		err_addr = ras->umc_ecc.ecc[channel_index].mca_umc_addr;

		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);



		/* translate umc channel address to soc pa, 3 parts are included */

		retired_page = ADDR_OF_8KB_BLOCK(err_addr) |

				ADDR_OF_256B_BLOCK(channel_index) |

				OFFSET_IN_256B_BLOCK(err_addr);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)

				== 1) {

			err_rec->address = err_addr;

			/* page frame address is saved */

			err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;

			err_rec->ts = (uint64_t)ktime_get_real_seconds();

			err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;

			err_rec->cu = 0;

			err_rec->mem_channel = channel_index;

			err_rec->mcumc_id = umc_inst;



			err_data->err_addr_cnt++;

		}

	}

}



static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev,

					     void *ras_error_status)

{

	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;



	uint32_t umc_inst        = 0;

	uint32_t ch_inst         = 0;

	uint32_t umc_reg_offset  = 0;



	/*TODO: driver needs to toggle DF Cstate to ensure

	 * safe access of UMC resgisters. Will add the protection

	 * when firmware interface is ready */

	LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {

		umc_reg_offset = get_umc_v6_7_reg_offset(adev,

							 umc_inst,

							 ch_inst);

		umc_v6_7_ecc_info_query_error_address(adev,

					     err_data,

					     umc_reg_offset,

					     ch_inst,

					     umc_inst);

	}

}



static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,

						   uint32_t umc_reg_offset,

						   unsigned long *error_count)
@@ -327,4 +486,6 @@ const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs = { 
	.query_ras_error_count = umc_v6_7_query_ras_error_count,

	.query_ras_error_address = umc_v6_7_query_ras_error_address,

	.query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,

	.ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count,

	.ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address,

};