Commit 885eb3fa authored by Jiansong Chen's avatar Jiansong Chen Committed by Alex Deucher
Browse files

drm/amdgpu: add gfx ip block for navy_flounder 



since navy_flounder has similar gc IP version with
sienna_cichlid, follow its setting for the moment.

Signed-off-by: default avatarJiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: default avatarTao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 026c396b

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −0
Original line number Diff line number Diff line
@@ -4118,6 +4118,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 
		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		adev->gfx.config.max_hw_contexts = 8;

		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;

		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4240,6 +4241,7 @@ static int gfx_v10_0_sw_init(void *handle) 
		adev->gfx.mec.num_queue_per_pipe = 8;

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		adev->gfx.me.num_me = 1;

		adev->gfx.me.num_pipe_per_me = 1;

		adev->gfx.me.num_queue_per_pipe = 1;
@@ -7093,6 +7095,7 @@ static int gfx_v10_0_early_init(void *handle) 
		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;

		break;

	default:
@@ -8590,6 +8593,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 
	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;

		break;

	case CHIP_NAVI12:

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −0
Original line number Diff line number Diff line
@@ -527,6 +527,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);

		break;

	default:

		return -EINVAL;