Commit 87891399 authored by Chris Morgan's avatar Chris Morgan Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add clk_rtc_32k to Anbernic xx3 Devices 



For the Anbernic devices to display properly, we need to specify the
clock frequency of the PLL_VPLL. Adding the parent clock in the
rk356x.dtsi requires us to update our clock definitions to accomplish
this.

Fixes: 64b69474 ("arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x")
Signed-off-by: default avatarChris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20230327153547.821822-1-macroalpha82@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent b37115b6

arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -16,8 +16,10 @@ 
};



&cru {

	assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;

	assigned-clock-rates = <1200000000>, <200000000>, <241500000>;

	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,

			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;

	assigned-clock-rates = <32768>, <1200000000>,

			       <200000000>, <241500000>;

};



&gpio_keys_control {

arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts

+4 −2
Original line number Diff line number Diff line
@@ -105,8 +105,10 @@ 
};



&cru {

	assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;

	assigned-clock-rates = <1200000000>, <200000000>, <500000000>;

	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,

			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;

	assigned-clock-rates = <32768>, <1200000000>,

			       <200000000>, <500000000>;

};



&dsi_dphy0 {