Commit b37115b6 authored Mar 17, 2023 by Sebastian Reichel Committed by Heiko Stuebner Mar 23, 2023

arm64: dts: rockchip: add rk3588 cache level information

Add missing, mandatory cache-level information for RK3588.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230317174102.61209-1-sebastian.reichel@collabora.com

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 78aedee1

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

+9 −0

Original line number	Diff line number	Diff line
		@@ -222,6 +222,7 @@
		cache-size = <131072>;
		cache-line-size = <64>;
		cache-sets = <512>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -230,6 +231,7 @@
		cache-size = <131072>;
		cache-line-size = <64>;
		cache-sets = <512>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -238,6 +240,7 @@
		cache-size = <131072>;
		cache-line-size = <64>;
		cache-sets = <512>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -246,6 +249,7 @@
		cache-size = <131072>;
		cache-line-size = <64>;
		cache-sets = <512>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -254,6 +258,7 @@
		cache-size = <524288>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -262,6 +267,7 @@
		cache-size = <524288>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -270,6 +276,7 @@
		cache-size = <524288>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -278,6 +285,7 @@
		cache-size = <524288>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-level = <2>;
		next-level-cache = <&l3_cache>;
		};

		@@ -286,6 +294,7 @@
		cache-size = <3145728>;
		cache-line-size = <64>;
		cache-sets = <4096>;
		cache-level = <3>;
		};
		};