Commit 86c82c8a authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy
Browse files

Revert "drm/i915/dg2: Tile 4 plane format support" 



Tile4 patch still needs an ack from userspace,
IGT tests and some essential fixes, related to
new .plane_caps attribute being added.

This reverts commit 3c542cfa.

Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Acked-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211124092355.16668-1-stanislav.lisovskiy@intel.com
parent 617ed6c2

drivers/gpu/drm/i915/display/intel_display.c

+0 −1
Original line number Diff line number Diff line
@@ -7769,7 +7769,6 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int 
		case I915_FORMAT_MOD_X_TILED:

		case I915_FORMAT_MOD_Y_TILED:

		case I915_FORMAT_MOD_Yf_TILED:

		case I915_FORMAT_MOD_4_TILED:

			break;

		default:

			drm_dbg_kms(&i915->drm,

drivers/gpu/drm/i915/display/intel_fb.c

+0 −9
Original line number Diff line number Diff line
@@ -139,9 +139,6 @@ struct intel_modifier_desc { 


static const struct intel_modifier_desc intel_modifiers[] = {

	{

		.modifier = I915_FORMAT_MOD_4_TILED,

		.display_ver = { 13, 13 },

	}, {

		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,

		.display_ver = { 12, 13 },

		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -547,12 +544,6 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 
			return 128;

		else

			return 512;

	case I915_FORMAT_MOD_4_TILED:

		/*

		 * Each 4K tile consists of 64B(8*8) subtiles, with

		 * same shape as Y Tile(i.e 4*16B OWords)

		 */

		return 128;

	case I915_FORMAT_MOD_Y_TILED_CCS:

		if (intel_fb_is_ccs_aux_plane(fb, color_plane))

			return 128;

drivers/gpu/drm/i915/display/intel_fbc.c

+0 −1
Original line number Diff line number Diff line
@@ -898,7 +898,6 @@ static bool tiling_is_valid(struct drm_i915_private *i915, 
	case I915_FORMAT_MOD_Y_TILED:

	case I915_FORMAT_MOD_Yf_TILED:

		return DISPLAY_VER(i915) >= 9;

	case I915_FORMAT_MOD_4_TILED:

	case I915_FORMAT_MOD_X_TILED:

		return true;

	default:

drivers/gpu/drm/i915/display/intel_plane_initial.c

+0 −1
Original line number Diff line number Diff line
@@ -125,7 +125,6 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 
	case DRM_FORMAT_MOD_LINEAR:

	case I915_FORMAT_MOD_X_TILED:

	case I915_FORMAT_MOD_Y_TILED:

	case I915_FORMAT_MOD_4_TILED:

		break;

	default:

		drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

+8 −12
Original line number Diff line number Diff line
@@ -751,8 +751,6 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) 
		return PLANE_CTL_TILED_X;

	case I915_FORMAT_MOD_Y_TILED:

		return PLANE_CTL_TILED_Y;

	case I915_FORMAT_MOD_4_TILED:

		return PLANE_CTL_TILED_4;

	case I915_FORMAT_MOD_Y_TILED_CCS:

	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:

		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1973,7 +1971,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 
	case DRM_FORMAT_Y216:

	case DRM_FORMAT_XVYU12_16161616:

	case DRM_FORMAT_XVYU16161616:

		if (!intel_fb_is_ccs_modifier(modifier))

		if (modifier == DRM_FORMAT_MOD_LINEAR ||

		    modifier == I915_FORMAT_MOD_X_TILED ||

		    modifier == I915_FORMAT_MOD_Y_TILED)

			return true;

		fallthrough;

	default:
@@ -2299,15 +2299,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, 
		else

			fb->modifier = I915_FORMAT_MOD_Y_TILED;

		break;

	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */

		if (HAS_4TILE(dev_priv)) {

			fb->modifier = I915_FORMAT_MOD_4_TILED;

		} else {

	case PLANE_CTL_TILED_YF:

		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)

			fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;

		else

			fb->modifier = I915_FORMAT_MOD_Yf_TILED;

		}

		break;

	default:

		MISSING_CASE(tiling);