Commit 3c542cfa authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy
Browse files

drm/i915/dg2: Tile 4 plane format support 



TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.

v2: - Fixed wrong case condition(Jani Nikula)
    - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)

v3: - s/I915_TILING_F/TILING_4/g
    - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
    - Removed unneeded fencing code

v4: - Rebased, fixed merge conflict with new table-oriented
      format modifier checking(Stan)
    - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)

v5: - Still had to remove some Tile F mentionings
    - Moved has_4tile from adlp to DG2(Ramalingam C)
    - Check specifically for DG2, but not the Display13(Imre)

v6: - Moved Tile4 associating struct for modifier/display to
      the beginning(Imre Deak)
    - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
      checks(Imre Deak)
    - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
      (Imre Deak)

v7: - Fixed display_ver to { 13, 13 }(Imre Deak)
    - Removed redundant newline(Imre Deak)

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJuha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211122211420.31584-1-stanislav.lisovskiy@intel.com
parent 448cc2fb

drivers/gpu/drm/i915/display/intel_display.c

+1 −0
Original line number Diff line number Diff line
@@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int 
		case I915_FORMAT_MOD_X_TILED:

		case I915_FORMAT_MOD_Y_TILED:

		case I915_FORMAT_MOD_Yf_TILED:

		case I915_FORMAT_MOD_4_TILED:

			break;

		default:

			drm_dbg_kms(&i915->drm,

drivers/gpu/drm/i915/display/intel_fb.c

+9 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ struct intel_modifier_desc { 


static const struct intel_modifier_desc intel_modifiers[] = {

	{

		.modifier = I915_FORMAT_MOD_4_TILED,

		.display_ver = { 13, 13 },

	}, {

		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,

		.display_ver = { 12, 13 },

		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 
			return 128;

		else

			return 512;

	case I915_FORMAT_MOD_4_TILED:

		/*

		 * Each 4K tile consists of 64B(8*8) subtiles, with

		 * same shape as Y Tile(i.e 4*16B OWords)

		 */

		return 128;

	case I915_FORMAT_MOD_Y_TILED_CCS:

		if (intel_fb_is_ccs_aux_plane(fb, color_plane))

			return 128;

drivers/gpu/drm/i915/display/intel_fbc.c

+1 −0
Original line number Diff line number Diff line
@@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915, 
	case I915_FORMAT_MOD_Y_TILED:

	case I915_FORMAT_MOD_Yf_TILED:

		return DISPLAY_VER(i915) >= 9;

	case I915_FORMAT_MOD_4_TILED:

	case I915_FORMAT_MOD_X_TILED:

		return true;

	default:

drivers/gpu/drm/i915/display/intel_plane_initial.c

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 
	case DRM_FORMAT_MOD_LINEAR:

	case I915_FORMAT_MOD_X_TILED:

	case I915_FORMAT_MOD_Y_TILED:

	case I915_FORMAT_MOD_4_TILED:

		break;

	default:

		drm_dbg(&dev_priv->drm,

drivers/gpu/drm/i915/display/skl_universal_plane.c

+12 −8
Original line number Diff line number Diff line
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier) 
		return PLANE_CTL_TILED_X;

	case I915_FORMAT_MOD_Y_TILED:

		return PLANE_CTL_TILED_Y;

	case I915_FORMAT_MOD_4_TILED:

		return PLANE_CTL_TILED_4;

	case I915_FORMAT_MOD_Y_TILED_CCS:

	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:

		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 
	case DRM_FORMAT_Y216:

	case DRM_FORMAT_XVYU12_16161616:

	case DRM_FORMAT_XVYU16161616:

		if (modifier == DRM_FORMAT_MOD_LINEAR ||

		    modifier == I915_FORMAT_MOD_X_TILED ||

		    modifier == I915_FORMAT_MOD_Y_TILED)

		if (!intel_fb_is_ccs_modifier(modifier))

			return true;

		fallthrough;

	default:
@@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, 
		else

			fb->modifier = I915_FORMAT_MOD_Y_TILED;

		break;

	case PLANE_CTL_TILED_YF:

	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */

		if (HAS_4TILE(dev_priv)) {

			fb->modifier = I915_FORMAT_MOD_4_TILED;

		} else {

			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)

				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;

			else

				fb->modifier = I915_FORMAT_MOD_Yf_TILED;

		}

		break;

	default:

		MISSING_CASE(tiling);