Commit 866147b8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC driver updates from Arnd Bergmann:
 "These are updates for drivers that are tied to a particular SoC,
  including the correspondig device tree bindings:

   - A couple of reset controller changes for unisoc, uniphier, renesas
     and zte platforms

   - memory controller driver fixes for omap and tegra

   - Rockchip io domain driver updates

   - Lots of updates for qualcomm platforms, mostly touching their
     firmware and power management drivers

   - Tegra FUSE and firmware driver updateѕ

   - Support for virtio transports in the SCMI firmware framework

   - cleanup of ixp4xx drivers, towards enabling multiplatform support
     and bringing it up to date with modern platforms

   - Minor updates for keystone, mediatek, omap, renesas"

* tag 'drivers-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits)
  reset: simple: remove ZTE details in Kconfig help
  soc: rockchip: io-domain: Remove unneeded semicolon
  soc: rockchip: io-domain: add rk3568 support
  dt-bindings: power: add rk3568-pmu-io-domain support
  bus: ixp4xx: return on error in ixp4xx_exp_probe()
  soc: renesas: Prefer memcpy() over strcpy()
  firmware: tegra: Stop using seq_get_buf()
  soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
  soc/tegra: fuse: Add runtime PM support
  soc/tegra: fuse: Clear fuse->clk on driver probe failure
  soc/tegra: pmc: Prevent racing with cpuilde driver
  soc/tegra: bpmp: Remove unused including <linux/version.h>
  dt-bindings: soc: ti: pruss: Add dma-coherent property
  soc: ti: Remove pm_runtime_irq_safe() usage for smartreflex
  soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM64x SoCs
  dt-bindings: soc: ti: pruss: Update bindings for K3 AM64x SoCs
  firmware: arm_scmi: Use WARN_ON() to check configured transports
  firmware: arm_scmi: Fix boolconv.cocci warnings
  soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing
  soc: mediatek: mmsys: add MT8365 support
  ...
parents 634135a0 06779631

Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel IXP4xx CompactFlash Card Controller



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



description: |

  The IXP4xx network processors have a CompactFlash interface that presents

  a CompactFlash card to the system as a true IDE (parallel ATA) device. The

  device is always connected to the expansion bus of the IXP4xx SoCs using one

  or two chip select areas and address translating logic on the board. The

  node must be placed inside a chip select node on the IXP4xx expansion bus.



properties:

  compatible:

    const: intel,ixp4xx-compact-flash



  reg:

    items:

      - description: Command interface registers

      - description: Control interface registers



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts



allOf:

  - $ref: pata-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    bus@c4000000 {

      compatible = "intel,ixp43x-expansion-bus-controller", "syscon";

      reg = <0xc4000000 0x1000>;

      native-endian;

      #address-cells = <2>;

      #size-cells = <1>;

      ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;

      dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;

      ide@1,0 {

        compatible = "intel,ixp4xx-compact-flash";

        reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;

        interrupt-parent = <&gpio0>;

        interrupts = <12 IRQ_TYPE_EDGE_RISING>;

      };

    };



...

Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel IXP4xx Expansion Bus Controller



description: |

  The IXP4xx expansion bus controller handles access to devices on the

  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,

  including IXP42x, IXP43x, IXP45x and IXP46x.



maintainers:

  - Linus Walleij <linus.walleij@linaro.org>



properties:

  $nodename:

    pattern: '^bus@[0-9a-f]+$'



  compatible:

    items:

      - enum:

          - intel,ixp42x-expansion-bus-controller

          - intel,ixp43x-expansion-bus-controller

          - intel,ixp45x-expansion-bus-controller

          - intel,ixp46x-expansion-bus-controller

      - const: syscon



  reg:

    description: Control registers for the expansion bus, these are not

      inside the memory range handled by the expansion bus.

    maxItems: 1



  native-endian:

    $ref: /schemas/types.yaml#/definitions/flag

    description: The IXP4xx has a peculiar MMIO access scheme, as it changes

      the access pattern for words (swizzling) on the bus depending on whether

      the SoC is running in big-endian or little-endian mode. Thus the

      registers must always be accessed using native endianness.



  "#address-cells":

    description: |

      The first cell is the chip select number.

      The second cell is the address offset within the bank.

    const: 2



  "#size-cells":

    const: 1



  ranges: true

  dma-ranges: true



patternProperties:

  "^.*@[0-7],[0-9a-f]+$":

    description: Devices attached to chip selects are represented as

      subnodes.

    type: object



    properties:

      intel,ixp4xx-eb-t1:

        description: Address timing, extend address phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 3



      intel,ixp4xx-eb-t2:

        description: Setup chip select timing, extend setup phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 3



      intel,ixp4xx-eb-t3:

        description: Strobe timing, extend strobe phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 15



      intel,ixp4xx-eb-t4:

        description: Hold timing, extend hold phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 3



      intel,ixp4xx-eb-t5:

        description: Recovery timing, extend recovery phase with n cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        maximum: 15



      intel,ixp4xx-eb-cycle-type:

        description: The type of cycles to use on the expansion bus for this

          chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1, 2]



      intel,ixp4xx-eb-byte-access-on-halfword:

        description: Allow byte read access on half word devices.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-hpi-hrdy-pol-high:

        description: Set HPI HRDY polarity to active high when using HPI.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-mux-address-and-data:

        description: Multiplex address and data on the data bus.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-ahb-split-transfers:

        description: Enable AHB split transfers.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-write-enable:

        description: Enable write cycles.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



      intel,ixp4xx-eb-byte-access:

        description: Expansion bus uses only 8 bits. The default is to use

          16 bits.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1]



required:

  - compatible

  - reg

  - native-endian

  - "#address-cells"

  - "#size-cells"

  - ranges

  - dma-ranges



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    bus@50000000 {

        compatible = "intel,ixp42x-expansion-bus-controller", "syscon";

        reg = <0xc4000000 0x28>;

        native-endian;

        #address-cells = <2>;

        #size-cells = <1>;

        ranges = <0 0x0 0x50000000 0x01000000>,

                 <1 0x0 0x51000000 0x01000000>;

        dma-ranges = <0 0x0 0x50000000 0x01000000>,

                     <1 0x0 0x51000000 0x01000000>;

        flash@0,0 {

            compatible = "intel,ixp4xx-flash", "cfi-flash";

            bank-width = <2>;

            reg = <0 0x00000000 0x1000000>;

            intel,ixp4xx-eb-t3 = <3>;

            intel,ixp4xx-eb-cycle-type = <0>;

            intel,ixp4xx-eb-byte-access-on-halfword = <1>;

            intel,ixp4xx-eb-write-enable = <1>;

            intel,ixp4xx-eb-byte-access = <0>;

        };

        serial@1,0 {

            compatible = "exar,xr16l2551", "ns8250";

            reg = <1 0x00000000 0x10>;

            interrupt-parent = <&gpio0>;

            interrupts = <4 IRQ_TYPE_LEVEL_LOW>;

            clock-frequency = <1843200>;

            intel,ixp4xx-eb-t3 = <3>;

            intel,ixp4xx-eb-cycle-type = <1>;

            intel,ixp4xx-eb-write-enable = <1>;

            intel,ixp4xx-eb-byte-access = <1>;

        };

    };

Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
      "fsl,imx53-sdma"

      "fsl,imx6q-sdma"

      "fsl,imx7d-sdma"

      "fsl,imx6ul-sdma"

      "fsl,imx8mq-sdma"

      "fsl,imx8mm-sdma"

      "fsl,imx8mn-sdma"

Documentation/devicetree/bindings/firmware/arm,scmi.yaml

+7 −1
Original line number Diff line number Diff line
@@ -34,6 +34,10 @@ properties: 
      - description: SCMI compliant firmware with ARM SMC/HVC transport

        items:

          - const: arm,scmi-smc

      - description: SCMI compliant firmware with SCMI Virtio transport.

                     The virtio transport only supports a single device.

        items:

          - const: arm,scmi-virtio



  interrupts:

    description:
@@ -172,6 +176,7 @@ patternProperties: 
      Each sub-node represents a protocol supported. If the platform

      supports a dedicated communication channel for a particular protocol,

      then the corresponding transport properties must be present.

      The virtio transport does not support a dedicated communication channel.



    properties:

      reg:
@@ -195,7 +200,6 @@ patternProperties: 


required:

  - compatible

  - shmem



if:

  properties:
@@ -209,6 +213,7 @@ then: 


  required:

    - mboxes

    - shmem



else:

  if:
@@ -219,6 +224,7 @@ else: 
  then:

    required:

      - arm,smc-id

      - shmem



examples:

  - |

Documentation/devicetree/bindings/power/qcom,rpmpd.yaml

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ properties: 
      - qcom,sc8180x-rpmhpd

      - qcom,sdm845-rpmhpd

      - qcom,sdx55-rpmhpd

      - qcom,sm6115-rpmpd

      - qcom,sm8150-rpmhpd

      - qcom,sm8250-rpmhpd

      - qcom,sm8350-rpmhpd