Unverified Commit 06779631 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'reset-for-v5.15' of git://git.pengutronix.de/pza/linux into arm/drivers 

Reset controller updates for v5.15

Add support for the SC7280 PDC Global and RZ/G2L USB/PHY reset
controllers, convert UniPhier glue device tree bindings to json-schema
and remove a leftover mention of ZTE zx2967 from Kconfig.

* tag 'reset-for-v5.15' of git://git.pengutronix.de/pza/linux:
  reset: simple: remove ZTE details in Kconfig help
  reset: renesas: Add RZ/G2L usbphy control driver
  dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
  dt-bindings: reset: Convert UniPhier glue reset to json-schema
  reset: qcom: Add PDC Global reset signals for WPSS
  dt-bindings: reset: pdc: Add PDC Global bindings
  dt-bindings: reset: aoss: Add AOSS reset controller binding

Link: https://lore.kernel.org/r/d42a75fc17ce718ef1b3fa4c5d3f5c7fb0bd2bc2.camel@pengutronix.de


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 9b3878a9 09f38243

Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml

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@@ -21,6 +21,11 @@ properties: 
          - const: "qcom,sc7180-aoss-cc"

          - const: "qcom,sdm845-aoss-cc"



      - description: on SC7280 SoCs the following compatibles must be specified

        items:

          - const: "qcom,sc7280-aoss-cc"

          - const: "qcom,sdm845-aoss-cc"



      - description: on SDM845 SoCs the following compatibles must be specified

        items:

          - const: "qcom,sdm845-aoss-cc"

Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml

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@@ -21,6 +21,10 @@ properties: 
          - const: "qcom,sc7180-pdc-global"

          - const: "qcom,sdm845-pdc-global"



      - description: on SC7280 SoCs the following compatibles must be specified

        items:

          - const: "qcom,sc7280-pdc-global"



      - description: on SDM845 SoCs the following compatibles must be specified

        items:

          - const: "qcom,sdm845-pdc-global"

Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L USBPHY Control



maintainers:

  - Biju Das <biju.das.jz@bp.renesas.com>



description:

  The RZ/G2L USBPHY Control mainly controls reset and power down of the

  USB/PHY.



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}

      - const: renesas,rzg2l-usbphy-ctrl



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



  power-domains:

    maxItems: 1



  '#reset-cells':

    const: 1

    description: |

      The phandle's argument in the reset specifier is the PHY reset associated

      with the USB port.

      0 = Port 1 Phy reset

      1 = Port 2 Phy reset



required:

  - compatible

  - reg

  - clocks

  - resets

  - power-domains

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r9a07g044-cpg.h>



    phyrst: usbphy-ctrl@11c40000 {

        compatible = "renesas,r9a07g044-usbphy-ctrl",

                     "renesas,rzg2l-usbphy-ctrl";

        reg = <0x11c40000 0x10000>;

        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;

        resets = <&cpg R9A07G044_USB_PRESETN>;

        power-domains = <&cpg>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Socionext UniPhier peripheral core reset in glue layer



description: |

  Some peripheral core reset belongs to its own glue layer. Before using

  this core reset, it is necessary to control the clocks and resets to

  enable this layer. These clocks and resets should be described in each

  property.



maintainers:

  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>



properties:

  compatible:

    enum:

      - socionext,uniphier-pro4-usb3-reset

      - socionext,uniphier-pro5-usb3-reset

      - socionext,uniphier-pxs2-usb3-reset

      - socionext,uniphier-ld20-usb3-reset

      - socionext,uniphier-pxs3-usb3-reset

      - socionext,uniphier-pro4-ahci-reset

      - socionext,uniphier-pxs2-ahci-reset

      - socionext,uniphier-pxs3-ahci-reset



  reg:

    maxItems: 1



  "#reset-cells":

    const: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    oneOf:

      - items:           # for Pro4, Pro5

          - const: gio

          - const: link

      - items:           # for others

          - const: link



  resets:

    minItems: 1

    maxItems: 2



  reset-names:

    oneOf:

      - items:           # for Pro4, Pro5

          - const: gio

          - const: link

      - items:           # for others

          - const: link



additionalProperties: false



required:

  - compatible

  - reg

  - "#reset-cells"

  - clocks

  - clock-names

  - resets

  - reset-names



examples:

  - |

    usb-glue@65b00000 {

        compatible = "simple-mfd";

        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0 0x65b00000 0x400>;



        usb_rst: reset@0 {

            compatible = "socionext,uniphier-ld20-usb3-reset";

            reg = <0x0 0x4>;

            #reset-cells = <1>;

            clock-names = "link";

            clocks = <&sys_clk 14>;

            reset-names = "link";

            resets = <&sys_rst 14>;

        };

    };

Documentation/devicetree/bindings/reset/uniphier-reset.txt

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UniPhier glue reset controller





Peripheral core reset in glue layer

-----------------------------------



Some peripheral core reset belongs to its own glue layer. Before using

this core reset, it is necessary to control the clocks and resets to enable

this layer. These clocks and resets should be described in each property.



Required properties:

- compatible: Should be

    "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3

    "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3

    "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3

    "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3

    "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3

    "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI

    "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI

    "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI

- #reset-cells: Should be 1.

- reg: Specifies offset and length of the register set for the device.

- clocks: A list of phandles to the clock gate for the glue layer.

	According to the clock-names, appropriate clocks are required.

- clock-names: Should contain

    "gio", "link" - for Pro4 and Pro5 SoCs

    "link"        - for others

- resets: A list of phandles to the reset control for the glue layer.

	According to the reset-names, appropriate resets are required.

- reset-names: Should contain

    "gio", "link" - for Pro4 and Pro5 SoCs

    "link"        - for others



Example:



	usb-glue@65b00000 {

		compatible = "socionext,uniphier-ld20-dwc3-glue",

			     "simple-mfd";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x65b00000 0x400>;



		usb_rst: reset@0 {

			compatible = "socionext,uniphier-ld20-usb3-reset";

			reg = <0x0 0x4>;

			#reset-cells = <1>;

			clock-names = "link";

			clocks = <&sys_clk 14>;

			reset-names = "link";

			resets = <&sys_rst 14>;

		};



		regulator {

			...

		};



		phy {

			...

		};

		...

	};