Commit 8630354f authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad settings 



BIT3 and BIT0 are reserved bits, should not touch.

Fixes: aec8ad34 ("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarRasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 242d8ee9

arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts

+20 −20
Original line number Diff line number Diff line
@@ -110,28 +110,28 @@ 
&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x19

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49

			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40

			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40

		>;

	};
@@ -151,7 +151,7 @@ 
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0

			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0

			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1

			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0

		>;

	};
@@ -163,13 +163,13 @@ 


	pinctrl_reg_usb1: regusb1grp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19

			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10

		>;

	};



	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41

			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40

		>;

	};

};