Commit 8440f575 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Pass the new context into disable OTG WA 



[Why]
When enabling an HPO stream for the first time after having previously
enabled a DIO stream there may be lingering DIO FIFO errors even though
the DIO is no longer enabled.

These can cause display clock change to hang if we don't apply the
OTG disable workaround since the ramping logic is tied to OTG on.

[How]
The workaround wasn't being applied in the sequence of:

1 DIO stream
0 streams
1 HPO stream

because current_state has no stream or planes in its context - and
it's only swapped after optimize has finished.

We should be using the incoming context instead to determine whether
this logic is needed or not.

Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0ec74408

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+4 −4
Original line number Diff line number Diff line
@@ -99,13 +99,13 @@ static int dcn31_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)

static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;
@@ -211,11 +211,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn31_disable_otg_wa(clk_mgr_base, true);

		dcn31_disable_otg_wa(clk_mgr_base, context, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn31_disable_otg_wa(clk_mgr_base, false);

		dcn31_disable_otg_wa(clk_mgr_base, context, false);



		update_dispclk = true;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+4 −4
Original line number Diff line number Diff line
@@ -81,13 +81,13 @@ static int dcn315_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)

static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;
@@ -175,11 +175,11 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn315_disable_otg_wa(clk_mgr_base, true);

		dcn315_disable_otg_wa(clk_mgr_base, context, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn315_disable_otg_wa(clk_mgr_base, false);

		dcn315_disable_otg_wa(clk_mgr_base, context, false);



		update_dispclk = true;

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+4 −4
Original line number Diff line number Diff line
@@ -112,13 +112,13 @@ static int dcn316_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;
@@ -221,11 +221,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn316_disable_otg_wa(clk_mgr_base, true);

		dcn316_disable_otg_wa(clk_mgr_base, context, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn316_disable_otg_wa(clk_mgr_base, false);

		dcn316_disable_otg_wa(clk_mgr_base, context, false);



		update_dispclk = true;

	}

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+1 −1
Original line number Diff line number Diff line
@@ -120,7 +120,7 @@ struct dccg_funcs { 


	void (*set_dtbclk_dto)(

			struct dccg *dccg,

			const struct dtbclk_dto_params *params);

			struct dtbclk_dto_params *dto_params);



	void (*set_audio_dtbclk_dto)(

			struct dccg *dccg,