Commit 0ec74408 authored by Leung, Martin's avatar Leung, Martin Committed by Alex Deucher
Browse files

drm/amd/display: revert Blank eDP on disable/enable drv 



why and how:
Revert this change. It was causing a black screen with certain blocks

Reviewed-by: default avatarGeorge Shen <George.Shen@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarLeung, Martin <Martin.Leung@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4b81dd2c

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+7 −1
Original line number Diff line number Diff line
@@ -638,8 +638,14 @@ static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base) 
	}

}



int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)

{

	return clk_mgr_base->clks.ref_dtbclk_khz;

}



static struct clk_mgr_funcs dcn31_funcs = {

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,

	.update_clocks = dcn31_update_clocks,

	.init_clocks = dcn31_init_clocks,

	.enable_pme_wa = dcn31_enable_pme_wa,
@@ -719,7 +725,7 @@ void dcn31_clk_mgr_construct( 
	}



	clk_mgr->base.base.dprefclk_khz = 600000;

	clk_mgr->base.dccg->ref_dtbclk_khz = 600000;

	clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

	dce_clock_read_ss_info(&clk_mgr->base);

	/*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/

	//clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

+2 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ void dcn31_clk_mgr_construct(struct dc_context *ctx, 
		struct pp_smu_funcs *pp_smu,

		struct dccg *dccg);



int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);



void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);



#endif //__DCN31_CLK_MGR_H__

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+3 −2
Original line number Diff line number Diff line
@@ -580,6 +580,7 @@ static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base) 


static struct clk_mgr_funcs dcn315_funcs = {

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,

	.update_clocks = dcn315_update_clocks,

	.init_clocks = dcn31_init_clocks,

	.enable_pme_wa = dcn315_enable_pme_wa,
@@ -656,9 +657,9 @@ void dcn315_clk_mgr_construct( 


	clk_mgr->base.base.dprefclk_khz = 600000;

	clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);

	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

	clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

	dce_clock_read_ss_info(&clk_mgr->base);

	clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);

	clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);



	clk_mgr->base.base.bw_params = &dcn315_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+2 −1
Original line number Diff line number Diff line
@@ -571,6 +571,7 @@ static void dcn316_clk_mgr_helper_populate_bw_params( 
static struct clk_mgr_funcs dcn316_funcs = {

	.enable_pme_wa = dcn316_enable_pme_wa,

	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,

	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,

	.update_clocks = dcn316_update_clocks,

	.init_clocks = dcn31_init_clocks,

	.are_clock_states_equal = dcn31_are_clock_states_equal,
@@ -685,7 +686,7 @@ void dcn316_clk_mgr_construct( 


	clk_mgr->base.base.dprefclk_khz = 600000;

	clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);

 	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

	clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

	dce_clock_read_ss_info(&clk_mgr->base);

	/*clk_mgr->base.dccg->ref_dtbclk_khz =

	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/

drivers/gpu/drm/amd/display/dc/dc.h

+3 −0
Original line number Diff line number Diff line
@@ -416,6 +416,7 @@ struct dc_clocks { 
	bool p_state_change_support;

	enum dcn_zstate_support_state zstate_support;

	bool dtbclk_en;

	int ref_dtbclk_khz;

	enum dcn_pwr_state pwr_state;

	/*

	 * Elements below are not compared for the purposes of
@@ -719,6 +720,8 @@ struct dc_debug_options { 
	bool apply_vendor_specific_lttpr_wa;

	bool extended_blank_optimization;

	union aux_wake_wa_options aux_wake_wa;

	/* uses value at boot and disables switch */

	bool disable_dtb_ref_clk_switch;

	uint8_t psr_power_use_phy_fsm;

	enum dml_hostvm_override_opts dml_hostvm_override;

};