Commit 4b81dd2c authored by Sherry Wang's avatar Sherry Wang Committed by Alex Deucher
Browse files

drm/amd/display: Read Golden Settings Table from VBIOS 



[Why]
Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table,
but driver will set it to default value 0x103d1110, which
causes issue in some case

[How]
Remove the driver code, use the value set by dmub in
dp_aux_init

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarSherry Wang <YAO.WANG1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bf23729c

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

+1 −3
Original line number Diff line number Diff line
@@ -230,9 +230,7 @@ static void enc31_hw_init(struct link_encoder *enc) 
	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3

	AUX_RX_DETECTION_THRESHOLD [30:28] = 1

*/

	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);



	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);

	// dmub will read AUX_DPHY_RX_CONTROL0/AUX_DPHY_TX_CONTROL from vbios table in dp_aux_init



	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;

	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk