Commit 83e9faac authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Clear optc false state when disable otg 



[why]
when disable optc, need to clear the underflow status as well.

Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 58e16c75

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

+7 −7
Original line number Diff line number Diff line
@@ -339,20 +339,20 @@ void dcn31_enable_power_gating_plane( 
	bool enable)

{

	bool force_on = true; /* disable power gating */

	uint32_t org_ip_request_cntl = 0;



	if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)

		force_on = false;



	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);

	if (org_ip_request_cntl == 0)

		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

	/* DCHUBP0/1/2/3/4/5 */

	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);

	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);

	/* DPP0/1/2/3/4/5 */

	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);

	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);



	force_on = true; /* disable power gating */

	if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
@@ -360,11 +360,11 @@ void dcn31_enable_power_gating_plane( 


	/* DCS0/1/2/3/4/5 */

	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);

	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);

	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

	REG_WAIT(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000);



	if (org_ip_request_cntl == 0)

		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

}



void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c

+4 −1
Original line number Diff line number Diff line
@@ -124,7 +124,6 @@ static bool optc31_enable_crtc(struct timing_generator *optc) 
static bool optc31_disable_crtc(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);



	/* disable otg request until end of the first line

	 * in the vertical blank region

	 */
@@ -138,6 +137,7 @@ static bool optc31_disable_crtc(struct timing_generator *optc) 
	REG_WAIT(OTG_CLOCK_CONTROL,

			OTG_BUSY, 0,

			1, 100000);

	optc1_clear_optc_underflow(optc);



	return true;

}
@@ -158,6 +158,9 @@ static bool optc31_immediate_disable_crtc(struct timing_generator *optc) 
			OTG_BUSY, 0,

			1, 100000);



	/* clear the false state */

	optc1_clear_optc_underflow(optc);



	return true;

}