Commit 58e16c75 authored by Roman Li's avatar Roman Li Committed by Alex Deucher
Browse files

drm/amd/display: Enable power gating before init_pipes 



[Why]
In init_hw() we call init_pipes() before enabling power gating.
init_pipes() tries to power gate dsc but it may fail because
required force-ons are not released yet.
As a result with dsc config the following errors observed on resume:
"REG_WAIT timeout 1us * 1000 tries - dcn20_dsc_pg_control"
"REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control"
"REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control"

[How]
Move enable_power_gating_plane() before init_pipes() in init_hw()

Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: default avatarEric Yang <Eric.Yang2@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarRoman Li <Roman.Li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95707203

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −2
Original line number Diff line number Diff line
@@ -1500,6 +1500,9 @@ void dcn10_init_hw(struct dc *dc) 
	/* we want to turn off all dp displays before doing detection */

	dc_link_blank_all_dp_displays(dc);



	if (hws->funcs.enable_power_gating_plane)

		hws->funcs.enable_power_gating_plane(dc->hwseq, true);



	/* If taking control over from VBIOS, we may want to optimize our first

	 * mode set, so we need to skip powering down pipes until we know which

	 * pipes we want to use.
@@ -1552,8 +1555,6 @@ void dcn10_init_hw(struct dc *dc) 


		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

	}

	if (hws->funcs.enable_power_gating_plane)

		hws->funcs.enable_power_gating_plane(dc->hwseq, true);



	if (dc->clk_mgr->funcs->notify_wm_ranges)

		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

+3 −2
Original line number Diff line number Diff line
@@ -547,6 +547,9 @@ void dcn30_init_hw(struct dc *dc) 
	/* we want to turn off all dp displays before doing detection */

	dc_link_blank_all_dp_displays(dc);



	if (hws->funcs.enable_power_gating_plane)

		hws->funcs.enable_power_gating_plane(dc->hwseq, true);



	/* If taking control over from VBIOS, we may want to optimize our first

	 * mode set, so we need to skip powering down pipes until we know which

	 * pipes we want to use.
@@ -624,8 +627,6 @@ void dcn30_init_hw(struct dc *dc) 


		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

	}

	if (hws->funcs.enable_power_gating_plane)

		hws->funcs.enable_power_gating_plane(dc->hwseq, true);



	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

+3 −2
Original line number Diff line number Diff line
@@ -199,6 +199,9 @@ void dcn31_init_hw(struct dc *dc) 
	/* we want to turn off all dp displays before doing detection */

	dc_link_blank_all_dp_displays(dc);



	if (hws->funcs.enable_power_gating_plane)

		hws->funcs.enable_power_gating_plane(dc->hwseq, true);



	/* If taking control over from VBIOS, we may want to optimize our first

	 * mode set, so we need to skip powering down pipes until we know which

	 * pipes we want to use.
@@ -248,8 +251,6 @@ void dcn31_init_hw(struct dc *dc) 


		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

	}

	if (hws->funcs.enable_power_gating_plane)

		hws->funcs.enable_power_gating_plane(dc->hwseq, true);



	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)

		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);