Commit 82bf0f18 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Only consider pixle rate div policy for DCN32+ 



[Why and How]
- Only consider pixel rate div policy for DCN32+

Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7ef41437

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

+2 −14
Original line number Diff line number Diff line
@@ -343,7 +343,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig 
{

	struct dc_stream_state *stream = pipe_ctx->stream;

	unsigned int odm_combine_factor = 0;

	struct dc *dc = pipe_ctx->stream->ctx->dc;

	bool two_pix_per_container = false;



	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
@@ -364,7 +363,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig 
		} else {

			*k1_div = PIXEL_RATE_DIV_BY_1;

			*k2_div = PIXEL_RATE_DIV_BY_4;

			if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy)

			if (odm_combine_factor == 2)

				*k2_div = PIXEL_RATE_DIV_BY_2;

		}

	}
@@ -384,21 +383,10 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) 
		return;



	odm_combine_factor = get_odm_config(pipe_ctx, NULL);

	if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1

		|| dcn314_is_dp_dig_pixel_rate_div_policy(pipe_ctx))

	if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1)

		pix_per_cycle = 2;



	if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)

		pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,

				pix_per_cycle);

}
 


bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)

{

	struct dc *dc = pipe_ctx->stream->ctx->dc;



	if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&

		dc->debug.enable_dp_dig_pixel_rate_div_policy)

		return true;

	return false;

}

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h

+0 −2
Original line number Diff line number Diff line
@@ -41,6 +41,4 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig 


void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);



bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);



#endif /* __DC_HWSS_DCN314_H__ */

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c

+0 −1
Original line number Diff line number Diff line
@@ -146,7 +146,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { 
	.setup_hpo_hw_control = dcn31_setup_hpo_hw_control,

	.calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values,

	.set_pixels_per_cycle = dcn314_set_pixels_per_cycle,

	.is_dp_dig_pixel_rate_div_policy = dcn314_is_dp_dig_pixel_rate_div_policy,

};



void dcn314_hw_sequencer_construct(struct dc *dc)