Commit 82a65f08 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-v6.6-1' of... 

Merge tag 'intel-pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel

 into devel

intel-pinctrl for v6.6-1

* New library driver for Intel MID to deduplicate code (Raag Jadav)
* Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav)
* Move most of the exported functions to the PINCTRL_INTEL namespace
* Make use of pm_ptr() in Bay Trail and Lynxpoint drivers
* Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers
* Consolidata ACPI dependency in Kconfig (Raag Jadav)
* Fix address_space_handler() argument in Cherryview driver (Raag Jadav)
* Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav)

The following is an automated git shortlog grouped by driver:

at91:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

baytrail:
 -  Make use of pm_ptr()
 -  reuse common functions from pinctrl-intel
 -  consolidate common mask operation

cherryview:
 -  fix address_space_handler() argument
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
 -  reuse common functions from pinctrl-intel

intel:
 -  consolidate ACPI dependency
 -  Switch to use exported namespace
 -  export common pinctrl functions

lynxpoint:
 -  Make use of pm_ptr()
 -  reuse common functions from pinctrl-intel

Merge patch series:
 - Merge patch series "Introduce Intel Tangier pinctrl driver"
 - Merge patch series "Reuse common functions from pinctrl-intel"

merrifield:
 -  Adapt to Intel Tangier driver

moorefield:
 -  Adapt to Intel Tangier driver

mvebu:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

pm:
 -  Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper

renesas:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

tangier:
 -  Introduce Intel Tangier driver

tegra:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 69657e60 d5301c90

drivers/pinctrl/intel/Kconfig

+3 −46
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# Intel pin control drivers

menu "Intel pinctrl drivers"

	depends on X86 || COMPILE_TEST

	depends on ACPI && (X86 || COMPILE_TEST)



config PINCTRL_BAYTRAIL

	bool "Intel Baytrail GPIO pin control"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  driver for memory mapped GPIO functionality on Intel Baytrail
@@ -17,7 +16,6 @@ config PINCTRL_BAYTRAIL 


config PINCTRL_CHERRYVIEW

	tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  Cherryview/Braswell pinctrl driver provides an interface that
@@ -25,39 +23,12 @@ config PINCTRL_CHERRYVIEW 


config PINCTRL_LYNXPOINT

	tristate "Intel Lynxpoint pinctrl and GPIO driver"

	depends on ACPI

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	select GPIOLIB

	select GPIOLIB_IRQCHIP

	select PINCTRL_INTEL

	help

	  Lynxpoint is the PCH of Intel Haswell. This pinctrl driver

	  provides an interface that allows configuring of PCH pins and

	  using them as GPIOs.



config PINCTRL_MERRIFIELD

	tristate "Intel Merrifield pinctrl driver"

	depends on X86_INTEL_MID

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	help

	  Merrifield Family-Level Interface Shim (FLIS) driver provides an

	  interface that allows configuring of SoC pins and using them as

	  GPIOs.



config PINCTRL_MOOREFIELD

	tristate "Intel Moorefield pinctrl driver"

	depends on X86_INTEL_MID

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	help

	  Moorefield Family-Level Interface Shim (FLIS) driver provides an

	  interface that allows configuring of SoC pins and using them as

	  GPIOs.



config PINCTRL_INTEL

	tristate

	select PINMUX
@@ -68,7 +39,6 @@ config PINCTRL_INTEL 


config PINCTRL_ALDERLAKE

	tristate "Intel Alder Lake pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -76,7 +46,6 @@ config PINCTRL_ALDERLAKE 


config PINCTRL_BROXTON

	tristate "Intel Broxton pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  Broxton pinctrl driver provides an interface that allows
@@ -84,7 +53,6 @@ config PINCTRL_BROXTON 


config PINCTRL_CANNONLAKE

	tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -92,7 +60,6 @@ config PINCTRL_CANNONLAKE 


config PINCTRL_CEDARFORK

	tristate "Intel Cedar Fork pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -100,7 +67,6 @@ config PINCTRL_CEDARFORK 


config PINCTRL_DENVERTON

	tristate "Intel Denverton pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -108,7 +74,6 @@ config PINCTRL_DENVERTON 


config PINCTRL_ELKHARTLAKE

	tristate "Intel Elkhart Lake SoC pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -116,7 +81,6 @@ config PINCTRL_ELKHARTLAKE 


config PINCTRL_EMMITSBURG

	tristate "Intel Emmitsburg pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -124,7 +88,6 @@ config PINCTRL_EMMITSBURG 


config PINCTRL_GEMINILAKE

	tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -132,7 +95,6 @@ config PINCTRL_GEMINILAKE 


config PINCTRL_ICELAKE

	tristate "Intel Ice Lake PCH pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -140,7 +102,6 @@ config PINCTRL_ICELAKE 


config PINCTRL_JASPERLAKE

	tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -148,7 +109,6 @@ config PINCTRL_JASPERLAKE 


config PINCTRL_LAKEFIELD

	tristate "Intel Lakefield SoC pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -156,7 +116,6 @@ config PINCTRL_LAKEFIELD 


config PINCTRL_LEWISBURG

	tristate "Intel Lewisburg pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -164,7 +123,6 @@ config PINCTRL_LEWISBURG 


config PINCTRL_METEORLAKE

	tristate "Intel Meteor Lake pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring
@@ -172,7 +130,6 @@ config PINCTRL_METEORLAKE 


config PINCTRL_SUNRISEPOINT

	tristate "Intel Sunrisepoint pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
@@ -181,10 +138,10 @@ config PINCTRL_SUNRISEPOINT 


config PINCTRL_TIGERLAKE

	tristate "Intel Tiger Lake pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring

	  of Intel Tiger Lake PCH pins and using them as GPIOs.



source "drivers/pinctrl/intel/Kconfig.tng"

endmenu

drivers/pinctrl/intel/Kconfig.tng

0 → 100644
+33 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

# Intel Tangier and compatible pin control drivers



if X86_INTEL_MID || COMPILE_TEST



config PINCTRL_TANGIER

	tristate

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

	help

	  This is a library driver for Intel Tangier pin controller and to

	  be selected and used by respective compatible platform drivers.



	  If built as a module its name will be pinctrl-tangier.



config PINCTRL_MERRIFIELD

	tristate "Intel Merrifield pinctrl driver"

	select PINCTRL_TANGIER

	help

	  Intel Merrifield Family-Level Interface Shim (FLIS) driver provides

	  an interface that allows configuring of SoC pins and using them as

	  GPIOs.



config PINCTRL_MOOREFIELD

	tristate "Intel Moorefield pinctrl driver"

	select PINCTRL_TANGIER

	help

	  Intel Moorefield Family-Level Interface Shim (FLIS) driver provides

	  an interface that allows configuring of SoC pins and using them as

	  GPIOs.



endif

drivers/pinctrl/intel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
obj-$(CONFIG_PINCTRL_BAYTRAIL)		+= pinctrl-baytrail.o

obj-$(CONFIG_PINCTRL_CHERRYVIEW)	+= pinctrl-cherryview.o

obj-$(CONFIG_PINCTRL_LYNXPOINT)		+= pinctrl-lynxpoint.o

obj-$(CONFIG_PINCTRL_TANGIER)		+= pinctrl-tangier.o

obj-$(CONFIG_PINCTRL_MERRIFIELD)	+= pinctrl-merrifield.o

obj-$(CONFIG_PINCTRL_MOOREFIELD)	+= pinctrl-moorefield.o

obj-$(CONFIG_PINCTRL_INTEL)		+= pinctrl-intel.o

drivers/pinctrl/intel/pinctrl-alderlake.c

+1 −0
Original line number Diff line number Diff line
@@ -748,3 +748,4 @@ module_platform_driver(adl_pinctrl_driver); 
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");

MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver");

MODULE_LICENSE("GPL v2");

MODULE_IMPORT_NS(PINCTRL_INTEL);

drivers/pinctrl/intel/pinctrl-baytrail.c

+29 −106
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/types.h>

#include <linux/platform_device.h>

#include <linux/pm_runtime.h>
@@ -551,25 +552,10 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 


static DEFINE_RAW_SPINLOCK(byt_lock);



static struct intel_community *byt_get_community(struct intel_pinctrl *vg,

						 unsigned int pin)

{

	struct intel_community *comm;

	int i;



	for (i = 0; i < vg->ncommunities; i++) {

		comm = vg->communities + i;

		if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)

			return comm;

	}



	return NULL;

}



static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,

				  int reg)

{

	struct intel_community *comm = byt_get_community(vg, offset);

	struct intel_community *comm = intel_get_community(vg, offset);

	u32 reg_offset;



	if (!comm)
@@ -591,68 +577,12 @@ static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 
	return comm->pad_regs + reg_offset + reg;

}



static int byt_get_groups_count(struct pinctrl_dev *pctldev)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);



	return vg->soc->ngroups;

}



static const char *byt_get_group_name(struct pinctrl_dev *pctldev,

				      unsigned int selector)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);



	return vg->soc->groups[selector].grp.name;

}



static int byt_get_group_pins(struct pinctrl_dev *pctldev,

			      unsigned int selector,

			      const unsigned int **pins,

			      unsigned int *num_pins)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);



	*pins		= vg->soc->groups[selector].grp.pins;

	*num_pins	= vg->soc->groups[selector].grp.npins;



	return 0;

}



static const struct pinctrl_ops byt_pinctrl_ops = {

	.get_groups_count	= byt_get_groups_count,

	.get_group_name		= byt_get_group_name,

	.get_group_pins		= byt_get_group_pins,

	.get_groups_count	= intel_get_groups_count,

	.get_group_name		= intel_get_group_name,

	.get_group_pins		= intel_get_group_pins,

};



static int byt_get_functions_count(struct pinctrl_dev *pctldev)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);



	return vg->soc->nfunctions;

}



static const char *byt_get_function_name(struct pinctrl_dev *pctldev,

					 unsigned int selector)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);



	return vg->soc->functions[selector].func.name;

}



static int byt_get_function_groups(struct pinctrl_dev *pctldev,

				   unsigned int selector,

				   const char * const **groups,

				   unsigned int *ngroups)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);



	*groups		= vg->soc->functions[selector].func.groups;

	*ngroups	= vg->soc->functions[selector].func.ngroups;



	return 0;

}



static void byt_set_group_simple_mux(struct intel_pinctrl *vg,

				     const struct intel_pingroup group,

				     unsigned int func)
@@ -851,9 +781,9 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 
}



static const struct pinmux_ops byt_pinmux_ops = {

	.get_functions_count	= byt_get_functions_count,

	.get_function_name	= byt_get_function_name,

	.get_function_groups	= byt_get_function_groups,

	.get_functions_count	= intel_get_functions_count,

	.get_function_name	= intel_get_function_name,

	.get_function_groups	= intel_get_function_groups,

	.set_mux		= byt_set_mux,

	.gpio_request_enable	= byt_gpio_request_enable,

	.gpio_disable_free	= byt_gpio_disable_free,
@@ -995,8 +925,8 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 
	void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);

	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);

	u32 conf, val, db_pulse, debounce;

	unsigned long flags;

	u32 conf, val, debounce;

	int i, ret = 0;



	raw_spin_lock_irqsave(&byt_lock, flags);
@@ -1053,8 +983,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 


			break;

		case PIN_CONFIG_INPUT_DEBOUNCE:

			debounce = readl(db_reg);



			if (arg)

				conf |= BYT_DEBOUNCE_EN;

			else
@@ -1062,32 +990,25 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 


			switch (arg) {

			case 375:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_375US;

				db_pulse = BYT_DEBOUNCE_PULSE_375US;

				break;

			case 750:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_750US;

				db_pulse = BYT_DEBOUNCE_PULSE_750US;

				break;

			case 1500:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_1500US;

				db_pulse = BYT_DEBOUNCE_PULSE_1500US;

				break;

			case 3000:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_3MS;

				db_pulse = BYT_DEBOUNCE_PULSE_3MS;

				break;

			case 6000:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_6MS;

				db_pulse = BYT_DEBOUNCE_PULSE_6MS;

				break;

			case 12000:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_12MS;

				db_pulse = BYT_DEBOUNCE_PULSE_12MS;

				break;

			case 24000:

				debounce &= ~BYT_DEBOUNCE_PULSE_MASK;

				debounce |= BYT_DEBOUNCE_PULSE_24MS;

				db_pulse = BYT_DEBOUNCE_PULSE_24MS;

				break;

			default:

				if (arg)
@@ -1095,8 +1016,13 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 
				break;

			}



			if (!ret)

			if (ret)

				break;



			debounce = readl(db_reg);

			debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;

			writel(debounce, db_reg);



			break;

		default:

			ret = -ENOTSUPP;
@@ -1265,7 +1191,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 
		val = readl(val_reg);

		raw_spin_unlock_irqrestore(&byt_lock, flags);



		comm = byt_get_community(vg, pin);

		comm = intel_get_community(vg, pin);

		if (!comm) {

			seq_printf(s, "Pin %i: can't retrieve community\n", pin);

			continue;
@@ -1733,7 +1659,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev) 
	return 0;

}



#ifdef CONFIG_PM_SLEEP

static int byt_gpio_suspend(struct device *dev)

{

	struct intel_pinctrl *vg = dev_get_drvdata(dev);
@@ -1817,9 +1742,7 @@ static int byt_gpio_resume(struct device *dev) 
	raw_spin_unlock_irqrestore(&byt_lock, flags);

	return 0;

}

#endif



#ifdef CONFIG_PM

static int byt_gpio_runtime_suspend(struct device *dev)

{

	return 0;
@@ -1829,19 +1752,17 @@ static int byt_gpio_runtime_resume(struct device *dev) 
{

	return 0;

}

#endif



static const struct dev_pm_ops byt_gpio_pm_ops = {

	SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)

	SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,

			   NULL)

	LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)

	RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL)

};



static struct platform_driver byt_gpio_driver = {

	.probe          = byt_pinctrl_probe,

	.driver         = {

		.name			= "byt_gpio",

		.pm			= &byt_gpio_pm_ops,

		.pm			= pm_ptr(&byt_gpio_pm_ops),

		.acpi_match_table	= byt_gpio_acpi_match,

		.suppress_bind_attrs	= true,

	},
@@ -1852,3 +1773,5 @@ static int __init byt_gpio_init(void) 
	return platform_driver_register(&byt_gpio_driver);

}

subsys_initcall(byt_gpio_init);



MODULE_IMPORT_NS(PINCTRL_INTEL);