Commit 8264ee69 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: drop unused code 



Those code were obsoleted by new common API
smu_cmn_to_asic_specific_index().

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6c339f37

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

+0 −119
Original line number Diff line number Diff line
@@ -207,118 +207,6 @@ static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_ 
	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),

};



static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_msg_mapping mapping;



	if (index >= SMU_MSG_MAX_COUNT)

		return -EINVAL;



	mapping = arcturus_message_map[index];

	if (!(mapping.valid_mapping))

		return -EINVAL;



	if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)

		return -EACCES;



	return mapping.map_to;

#endif

	return 0;

}



static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_CLK_COUNT)

		return -EINVAL;



	mapping = arcturus_clk_map[index];

	if (!(mapping.valid_mapping)) {

		dev_warn(smc->adev->dev, "Unsupported SMU clk: %d\n", index);

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_FEATURE_COUNT)

		return -EINVAL;



	mapping = arcturus_feature_mask_map[index];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_TABLE_COUNT)

		return -EINVAL;



	mapping = arcturus_table_map[index];

	if (!(mapping.valid_mapping)) {

		dev_warn(smc->adev->dev, "Unsupported SMU table: %d\n", index);

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_POWER_SOURCE_COUNT)

		return -EINVAL;



	mapping = arcturus_pwr_src_map[index];

	if (!(mapping.valid_mapping)) {

		dev_warn(smc->adev->dev, "Unsupported SMU power source: %d\n", index);

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)

		return -EINVAL;



	mapping = arcturus_workload_map[profile];

	if (!(mapping.valid_mapping))

		return -EINVAL;



	return mapping.map_to;

#endif

	return 0;

}



static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)

{

	struct smu_table_context *smu_table = &smu->smu_table;
@@ -2349,13 +2237,6 @@ static void arcturus_log_thermal_throttling_event(struct smu_context *smu) 
}



static const struct pptable_funcs arcturus_ppt_funcs = {

	/* translate smu index into arcturus specific index */

	.get_smu_msg_index = arcturus_get_smu_msg_index,

	.get_smu_clk_index = arcturus_get_smu_clk_index,

	.get_smu_feature_index = arcturus_get_smu_feature_index,

	.get_smu_table_index = arcturus_get_smu_table_index,

	.get_smu_power_index= arcturus_get_pwr_src_index,

	.get_workload_type = arcturus_get_workload_type,

	/* internal structurs allocations */

	.tables_init = arcturus_tables_init,

	.alloc_dpm_context = arcturus_allocate_dpm_context,

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+0 −6
Original line number Diff line number Diff line
@@ -452,12 +452,6 @@ struct i2c_adapter; 


struct pptable_funcs {

	int (*alloc_dpm_context)(struct smu_context *smu);

	int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);

	int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);

	int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);

	int (*run_btc)(struct smu_context *smu);

	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);

	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+0 −11
Original line number Diff line number Diff line
@@ -62,17 +62,6 @@ static const struct smu_temperature_range smu11_thermal_policy[] = 
	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},

};



struct smu_11_0_msg_mapping {

	int	valid_mapping;

	int	map_to;

	int	valid_in_vf;

};



struct smu_11_0_cmn2aisc_mapping {

	int	valid_mapping;

	int	map_to;

};



struct smu_11_0_max_sustainable_clocks {

	uint32_t display_clock;

	uint32_t phy_clock;

drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h

+0 −6
Original line number Diff line number Diff line
@@ -31,12 +31,6 @@ 
#define MP1_Public			0x03b00000

#define MP1_SRAM			0x03c00004





struct smu_12_0_cmn2aisc_mapping {

	int	valid_mapping;

	int	map_to;

};



int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,

					      uint16_t msg);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+0 −118
Original line number Diff line number Diff line
@@ -227,118 +227,6 @@ static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = 
	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),

};



static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_msg_mapping mapping;



	if (index >= SMU_MSG_MAX_COUNT)

		return -EINVAL;



	mapping = navi10_message_map[index];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)

		return -EACCES;



	return mapping.map_to;

#endif

	return 0;

}



static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_CLK_COUNT)

		return -EINVAL;



	mapping = navi10_clk_map[index];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_FEATURE_COUNT)

		return -EINVAL;



	mapping = navi10_feature_mask_map[index];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_TABLE_COUNT)

		return -EINVAL;



	mapping = navi10_table_map[index];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (index >= SMU_POWER_SOURCE_COUNT)

		return -EINVAL;



	mapping = navi10_pwr_src_map[index];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}





static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)

{

#if 0

	struct smu_11_0_cmn2aisc_mapping mapping;



	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)

		return -EINVAL;



	mapping = navi10_workload_map[profile];

	if (!(mapping.valid_mapping)) {

		return -EINVAL;

	}



	return mapping.map_to;

#endif

	return 0;

}



static bool is_asic_secure(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;
@@ -2368,12 +2256,6 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu) 
static const struct pptable_funcs navi10_ppt_funcs = {

	.tables_init = navi10_tables_init,

	.alloc_dpm_context = navi10_allocate_dpm_context,

	.get_smu_msg_index = navi10_get_smu_msg_index,

	.get_smu_clk_index = navi10_get_smu_clk_index,

	.get_smu_feature_index = navi10_get_smu_feature_index,

	.get_smu_table_index = navi10_get_smu_table_index,

	.get_smu_power_index = navi10_get_pwr_src_index,

	.get_workload_type = navi10_get_workload_type,

	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,

	.set_default_dpm_table = navi10_set_default_dpm_table,

	.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,