Commit 6c339f37 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: unify swSMU index to asic specific index mapping



By this we can drop redundant code.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 22f2447c
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+3 −1
Original line number Diff line number Diff line
@@ -35,7 +35,9 @@ AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(

include $(AMD_POWERPLAY)

POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o sienna_cichlid_ppt.o
POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o \
	    smu_v12_0.o arcturus_ppt.o navi10_ppt.o \
	    renoir_ppt.o sienna_cichlid_ppt.o smu_cmn.o

AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))

+22 −7
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@
#include "sienna_cichlid_ppt.h"
#include "renoir_ppt.h"
#include "amd_pcie.h"
#include "smu_cmn.h"

/*
 * DO NOT use these for err/warn/info/debug messages.
@@ -94,7 +95,9 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
			feature_mask[1], feature_mask[0]);

	for (i = 0; i < SMU_FEATURE_COUNT; i++) {
		feature_index = smu_feature_get_index(smu, i);
		feature_index = smu_cmn_to_asic_specific_index(smu,
							       CMN2ASIC_MAPPING_FEATURE,
							       i);
		if (feature_index < 0)
			continue;
		sort_feature[feature_index] = i;
@@ -405,7 +408,9 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int
	struct smu_table_context *smu_table = &smu->smu_table;
	struct amdgpu_device *adev = smu->adev;
	struct smu_table *table = &smu_table->driver_table;
	int table_id = smu_table_get_index(smu, table_index);
	int table_id = smu_cmn_to_asic_specific_index(smu,
						      CMN2ASIC_MAPPING_TABLE,
						      table_index);
	uint32_t table_size;
	int ret = 0;
	if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
@@ -546,7 +551,9 @@ int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)

	if (smu->is_apu)
		return 1;
	feature_id = smu_feature_get_index(smu, mask);
	feature_id = smu_cmn_to_asic_specific_index(smu,
						    CMN2ASIC_MAPPING_FEATURE,
						    mask);
	if (feature_id < 0)
		return 0;

@@ -565,7 +572,9 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
	struct smu_feature *feature = &smu->smu_feature;
	int feature_id;

	feature_id = smu_feature_get_index(smu, mask);
	feature_id = smu_cmn_to_asic_specific_index(smu,
						    CMN2ASIC_MAPPING_FEATURE,
						    mask);
	if (feature_id < 0)
		return -EINVAL;

@@ -582,7 +591,9 @@ int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask
	int feature_id;
	int ret = 0;

	feature_id = smu_feature_get_index(smu, mask);
	feature_id = smu_cmn_to_asic_specific_index(smu,
						    CMN2ASIC_MAPPING_FEATURE,
						    mask);
	if (feature_id < 0)
		return 0;

@@ -1314,7 +1325,9 @@ static int smu_disable_dpms(struct smu_context *smu)
	 */
	if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
		features_to_disable = U64_MAX &
			~(1ULL << smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT));
			~(1ULL << smu_cmn_to_asic_specific_index(smu,
							CMN2ASIC_MAPPING_FEATURE,
							SMU_FEATURE_BACO_BIT));
		ret = smu_feature_update_enable_state(smu,
						      features_to_disable,
						      0);
@@ -1882,7 +1895,9 @@ int smu_set_mp1_state(struct smu_context *smu,
	}

	/* some asics may not support those messages */
	if (smu_msg_get_index(smu, msg) < 0) {
	if (smu_cmn_to_asic_specific_index(smu,
					   CMN2ASIC_MAPPING_MSG,
					   msg) < 0) {
		mutex_unlock(&smu->mutex);
		return 0;
	}
+40 −11
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@
#include <linux/i2c.h>
#include <linux/pci.h>
#include "amdgpu_ras.h"
#include "smu_cmn.h"

/*
 * DO NOT use these for err/warn/info/debug messages.
@@ -57,8 +58,6 @@

#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))

#define MSG_MAP(msg, index, valid_in_vf) \
	[SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
	[smu_feature] = {1, (arcturus_feature)}

@@ -79,7 +78,7 @@
/* possible frequency drift (1Mhz) */
#define EPSILON				1

static struct smu_11_0_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion,			1),
	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion,		1),
@@ -142,7 +141,7 @@ static struct smu_11_0_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
	MSG_MAP(ReadSerialNumBottom32,		     PPSMC_MSG_ReadSerialNumBottom32,		1),
};

static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
	CLK_MAP(SCLK,	PPCLK_GFXCLK),
	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
@@ -153,7 +152,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
	CLK_MAP(VCLK, PPCLK_VCLK),
};

static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
	FEA_MAP(DPM_PREFETCHER),
	FEA_MAP(DPM_GFXCLK),
	FEA_MAP(DPM_UCLK),
@@ -182,7 +181,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_CO
	FEA_MAP(TEMP_DEPENDENT_VMIN),
};

static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
	TAB_MAP(PPTABLE),
	TAB_MAP(AVFS),
	TAB_MAP(AVFS_PSM_DEBUG),
@@ -195,12 +194,12 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
	TAB_MAP(ACTIVITY_MONITOR_COEFF),
};

static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
	PWR_MAP(AC),
	PWR_MAP(DC),
};

static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
@@ -210,6 +209,7 @@ static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFI

static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
{
#if 0
	struct smu_11_0_msg_mapping mapping;

	if (index >= SMU_MSG_MAX_COUNT)
@@ -223,10 +223,13 @@ static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
		return -EACCES;

	return mapping.map_to;
#endif
	return 0;
}

static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
{
#if 0
	struct smu_11_0_cmn2aisc_mapping mapping;

	if (index >= SMU_CLK_COUNT)
@@ -239,10 +242,13 @@ static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
	}

	return mapping.map_to;
#endif
	return 0;
}

static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
{
#if 0
	struct smu_11_0_cmn2aisc_mapping mapping;

	if (index >= SMU_FEATURE_COUNT)
@@ -254,10 +260,13 @@ static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t inde
	}

	return mapping.map_to;
#endif
	return 0;
}

static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
{
#if 0
	struct smu_11_0_cmn2aisc_mapping mapping;

	if (index >= SMU_TABLE_COUNT)
@@ -270,10 +279,13 @@ static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
	}

	return mapping.map_to;
#endif
	return 0;
}

static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
{
#if 0
	struct smu_11_0_cmn2aisc_mapping mapping;

	if (index >= SMU_POWER_SOURCE_COUNT)
@@ -286,10 +298,13 @@ static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
	}

	return mapping.map_to;
#endif
	return 0;
}

static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
#if 0
	struct smu_11_0_cmn2aisc_mapping mapping;

	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
@@ -300,6 +315,8 @@ static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER
		return -EINVAL;

	return mapping.map_to;
#endif
	return 0;
}

static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
@@ -731,7 +748,9 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
	if (!value)
		return -EINVAL;

	clk_id = smu_clk_get_index(smu, clk_type);
	clk_id = smu_cmn_to_asic_specific_index(smu,
						CMN2ASIC_MAPPING_CLK,
						clk_type);
	if (clk_id < 0)
		return -EINVAL;

@@ -1301,7 +1320,9 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
		 * Not all profile modes are supported on arcturus.
		 */
		workload_type = smu_workload_get_type(smu, i);
		workload_type = smu_cmn_to_asic_specific_index(smu,
							       CMN2ASIC_MAPPING_WORKLOAD,
							       i);
		if (workload_type < 0)
			continue;

@@ -1425,7 +1446,9 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu,
	 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
	 * Not all profile modes are supported on arcturus.
	 */
	workload_type = smu_workload_get_type(smu, profile_mode);
	workload_type = smu_cmn_to_asic_specific_index(smu,
						       CMN2ASIC_MAPPING_WORKLOAD,
						       profile_mode);
	if (workload_type < 0) {
		dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
		return -EINVAL;
@@ -2412,4 +2435,10 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
void arcturus_set_ppt_funcs(struct smu_context *smu)
{
	smu->ppt_funcs = &arcturus_ppt_funcs;
	smu->message_map = arcturus_message_map;
	smu->clock_map = arcturus_clk_map;
	smu->feature_map = arcturus_feature_mask_map;
	smu->table_map = arcturus_table_map;
	smu->pwr_src_map = arcturus_pwr_src_map;
	smu->workload_map = arcturus_workload_map;
}
+50 −0
Original line number Diff line number Diff line
@@ -366,6 +366,17 @@ struct smu_umd_pstate_table {
	struct pstates_clk_freq		dclk_pstate;
};

struct cmn2asic_msg_mapping {
	int	valid_mapping;
	int	map_to;
	int	valid_in_vf;
};

struct cmn2asic_mapping {
	int	valid_mapping;
	int	map_to;
};

#define WORKLOAD_POLICY_MAX 7
struct smu_context
{
@@ -373,6 +384,12 @@ struct smu_context
	struct amdgpu_irq_src		irq_source;

	const struct pptable_funcs	*ppt_funcs;
	const struct cmn2asic_msg_mapping	*message_map;
	const struct cmn2asic_mapping	*clock_map;
	const struct cmn2asic_mapping	*feature_map;
	const struct cmn2asic_mapping	*table_map;
	const struct cmn2asic_mapping	*pwr_src_map;
	const struct cmn2asic_mapping	*workload_map;
	struct mutex			mutex;
	struct mutex			sensor_lock;
	struct mutex			metrics_lock;
@@ -604,6 +621,39 @@ typedef enum {
	METRICS_CURR_FANSPEED,
} MetricsMember_t;

enum smu_cmn2asic_mapping_type {
	CMN2ASIC_MAPPING_MSG,
	CMN2ASIC_MAPPING_CLK,
	CMN2ASIC_MAPPING_FEATURE,
	CMN2ASIC_MAPPING_TABLE,
	CMN2ASIC_MAPPING_PWR,
	CMN2ASIC_MAPPING_WORKLOAD,
};

#define MSG_MAP(msg, index, valid_in_vf) \
	[SMU_MSG_##msg] = {1, (index), (valid_in_vf)}

#define CLK_MAP(clk, index) \
	[SMU_##clk] = {1, (index)}

#define FEA_MAP(fea) \
	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}

#define TAB_MAP(tab) \
	[SMU_TABLE_##tab] = {1, TABLE_##tab}

#define TAB_MAP_VALID(tab) \
	[SMU_TABLE_##tab] = {1, TABLE_##tab}

#define TAB_MAP_INVALID(tab) \
	[SMU_TABLE_##tab] = {0, TABLE_##tab}

#define PWR_MAP(tab) \
	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}

#define WORKLOAD_MAP(profile, workload) \
	[profile] = {1, (workload)}

int smu_load_microcode(struct smu_context *smu);

int smu_check_fw_status(struct smu_context *smu);
+0 −15
Original line number Diff line number Diff line
@@ -52,21 +52,6 @@
#define MAX_DPM_LEVELS 16
#define MAX_PCIE_CONF 2

#define CLK_MAP(clk, index) \
	[SMU_##clk] = {1, (index)}

#define FEA_MAP(fea) \
	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}

#define TAB_MAP(tab) \
	[SMU_TABLE_##tab] = {1, TABLE_##tab}

#define PWR_MAP(tab) \
	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}

#define WORKLOAD_MAP(profile, workload) \
	[profile] = {1, (workload)}

#define CTF_OFFSET_EDGE			5
#define CTF_OFFSET_HOTSPOT		5
#define CTF_OFFSET_MEM			5
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