Commit 80d2229b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi: drop global msm_dsi_phy_type enumaration 



With the current upstream driver the msm_dsi_phy_type enum does not make
much sense: all DSI PHYs are probed using the dt bindings, the phy type
is not passed between drivers. Use quirks in phy individual PHY drivers
to differentiate minor harware differences and drop the enum.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-8-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 93cf7d62

drivers/gpu/drm/msm/dsi/dsi.h

+0 −12
Original line number Diff line number Diff line
@@ -23,18 +23,6 @@ 
struct msm_dsi_phy_shared_timings;

struct msm_dsi_phy_clk_request;



enum msm_dsi_phy_type {

	MSM_DSI_PHY_28NM_HPM,

	MSM_DSI_PHY_28NM_LP,

	MSM_DSI_PHY_20NM,

	MSM_DSI_PHY_28NM_8960,

	MSM_DSI_PHY_14NM,

	MSM_DSI_PHY_10NM,

	MSM_DSI_PHY_7NM,

	MSM_DSI_PHY_7NM_V4_1,

	MSM_DSI_PHY_MAX

};



enum msm_dsi_phy_usecase {

	MSM_DSI_PHY_STANDALONE,

	MSM_DSI_PHY_MASTER,

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+0 −4
Original line number Diff line number Diff line
@@ -13,9 +13,6 @@ 
#define dsi_phy_read(offset) msm_readl((offset))

#define dsi_phy_write(offset, data) msm_writel((data), (offset))



/* v3.0.0 10nm implementation that requires the old timings settings */

#define V3_0_0_10NM_OLD_TIMINGS_QUIRK	BIT(0)



struct msm_dsi_phy_ops {

	int (*pll_init)(struct msm_dsi_phy *phy);

	int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
@@ -37,7 +34,6 @@ struct msm_dsi_pll_ops { 
};



struct msm_dsi_phy_cfg {

	enum msm_dsi_phy_type type;

	struct dsi_reg_config reg_cfg;

	struct msm_dsi_phy_ops ops;

	const struct msm_dsi_pll_ops pll_ops;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+6 −5
Original line number Diff line number Diff line
@@ -59,6 +59,9 @@ struct dsi_pll_regs { 
	u32 ssc_control;

};



/* v3.0.0 10nm implementation that requires the old timings settings */

#define DSI_PHY_10NM_QUIRK_OLD_TIMINGS	BIT(0)



struct dsi_pll_config {

	u32 ref_freq;

	bool div_override;
@@ -915,7 +918,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) 
	u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };

	void __iomem *lane_base = phy->lane_base;



	if (phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)

	if (phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)

		tx_dctrl[3] = 0x02;



	/* Strength ctrl settings */
@@ -950,7 +953,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy) 
			      tx_dctrl[i]);

	}



	if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) {

	if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) {

		/* Toggle BIT 0 to release freeze I/0 */

		dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);

		dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
@@ -1090,7 +1093,6 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy) 
}



const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {

	.type = MSM_DSI_PHY_10NM,

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.reg_cfg = {
@@ -1116,7 +1118,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { 
};



const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {

	.type = MSM_DSI_PHY_10NM,

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.reg_cfg = {
@@ -1139,5 +1140,5 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { 
	},

	.io_start = { 0xc994400, 0xc996400 },

	.num_dsi_phy = 2,

	.quirks = V3_0_0_10NM_OLD_TIMINGS_QUIRK,

	.quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,

};

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+0 −2
Original line number Diff line number Diff line
@@ -1215,7 +1215,6 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) 
}



const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {

	.type = MSM_DSI_PHY_14NM,

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.reg_cfg = {
@@ -1243,7 +1242,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 
};



const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {

	.type = MSM_DSI_PHY_14NM,

	.src_pll_truthtable = { {false, false}, {true, false} },

	.has_phy_lane = true,

	.reg_cfg = {

drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c

+0 −1
Original line number Diff line number Diff line
@@ -125,7 +125,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) 
}



const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {

	.type = MSM_DSI_PHY_20NM,

	.src_pll_truthtable = { {false, true}, {false, true} },

	.has_phy_regulator = true,

	.reg_cfg = {