Commit 93cf7d62 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi: move all PLL callbacks into PHY config struct 



Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits
the amount of data in the struct msm_dsi_pll.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-7-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 6a58cfec

drivers/gpu/drm/msm/dsi/dsi.h

+0 −6
Original line number Diff line number Diff line
@@ -107,8 +107,6 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi *msm_dsi); 
/* dsi pll */

struct msm_dsi_pll;

#ifdef CONFIG_DRM_MSM_DSI_PLL

struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,

			enum msm_dsi_phy_type type, int dsi_id);

void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);

int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,

	struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
@@ -117,10 +115,6 @@ int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); 
int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,

			    enum msm_dsi_phy_usecase uc);

#else

static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,

			 enum msm_dsi_phy_type type, int id) {

	return ERR_PTR(-ENODEV);

}

static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)

{

}

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+8 −6
Original line number Diff line number Diff line
@@ -709,12 +709,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 
	if (ret)

		goto fail;



	phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);

	if (IS_ERR_OR_NULL(phy->pll)) {

	if (phy->cfg->ops.pll_init) {

		ret = phy->cfg->ops.pll_init(phy);

		if (ret) {

			DRM_DEV_INFO(dev,

			"%s: pll init failed: %ld, need separate pll clk driver\n",

			__func__, PTR_ERR(phy->pll));

		phy->pll = NULL;

				"%s: pll init failed: %d, need separate pll clk driver\n",

				__func__, ret);

			goto fail;

		}

	}



	dsi_phy_disable_resource(phy);

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+15 −0
Original line number Diff line number Diff line
@@ -17,15 +17,30 @@ 
#define V3_0_0_10NM_OLD_TIMINGS_QUIRK	BIT(0)



struct msm_dsi_phy_ops {

	int (*pll_init)(struct msm_dsi_phy *phy);

	int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,

			struct msm_dsi_phy_clk_request *clk_req);

	void (*disable)(struct msm_dsi_phy *phy);

};



struct msm_dsi_pll_ops {

	int (*enable_seq)(struct msm_dsi_pll *pll);

	void (*disable_seq)(struct msm_dsi_pll *pll);

	int (*get_provider)(struct msm_dsi_pll *pll,

			struct clk **byte_clk_provider,

			struct clk **pixel_clk_provider);

	void (*destroy)(struct msm_dsi_pll *pll);

	void (*save_state)(struct msm_dsi_pll *pll);

	int (*restore_state)(struct msm_dsi_pll *pll);

	int (*set_usecase)(struct msm_dsi_pll *pll,

			   enum msm_dsi_phy_usecase uc);

};



struct msm_dsi_phy_cfg {

	enum msm_dsi_phy_type type;

	struct dsi_reg_config reg_cfg;

	struct msm_dsi_phy_ops ops;

	const struct msm_dsi_pll_ops pll_ops;



	/*

	 * Each cell {phy_id, pll_id} of the truth table indicates

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+27 −11
Original line number Diff line number Diff line
@@ -828,15 +828,17 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) 
	return ret;

}



struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)

static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)

{

	struct platform_device *pdev = phy->pdev;

	int id = phy->id;

	struct dsi_pll_10nm *pll_10nm;

	struct msm_dsi_pll *pll;

	int ret;



	pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);

	if (!pll_10nm)

		return ERR_PTR(-ENOMEM);

		return -ENOMEM;



	DBG("DSI PLL%d", id);
@@ -847,13 +849,13 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) 
	pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");

	if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");

		return ERR_PTR(-ENOMEM);

		return -ENOMEM;

	}



	pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");

	if (IS_ERR_OR_NULL(pll_10nm->mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");

		return ERR_PTR(-ENOMEM);

		return -ENOMEM;

	}



	spin_lock_init(&pll_10nm->postdiv_lock);
@@ -861,24 +863,22 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) 
	pll = &pll_10nm->base;

	pll->min_rate = 1000000000UL;

	pll->max_rate = 3500000000UL;

	pll->get_provider = dsi_pll_10nm_get_provider;

	pll->destroy = dsi_pll_10nm_destroy;

	pll->save_state = dsi_pll_10nm_save_state;

	pll->restore_state = dsi_pll_10nm_restore_state;

	pll->set_usecase = dsi_pll_10nm_set_usecase;

	pll->cfg = phy->cfg;



	pll_10nm->vco_delay = 1;



	ret = pll_10nm_register(pll_10nm);

	if (ret) {

		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);

		return ERR_PTR(ret);

		return ret;

	}



	phy->pll = pll;



	/* TODO: Remove this when we have proper display handover support */

	msm_dsi_pll_save_state(pll);



	return pll;

	return 0;

}



static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy)
@@ -1102,6 +1102,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { 
	.ops = {

		.enable = dsi_10nm_phy_enable,

		.disable = dsi_10nm_phy_disable,

		.pll_init = dsi_pll_10nm_init,

	},

	.pll_ops = {

		.get_provider = dsi_pll_10nm_get_provider,

		.destroy = dsi_pll_10nm_destroy,

		.save_state = dsi_pll_10nm_save_state,

		.restore_state = dsi_pll_10nm_restore_state,

		.set_usecase = dsi_pll_10nm_set_usecase,

	},

	.io_start = { 0xae94400, 0xae96400 },

	.num_dsi_phy = 2,
@@ -1120,6 +1128,14 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { 
	.ops = {

		.enable = dsi_10nm_phy_enable,

		.disable = dsi_10nm_phy_disable,

		.pll_init = dsi_pll_10nm_init,

	},

	.pll_ops = {

		.get_provider = dsi_pll_10nm_get_provider,

		.destroy = dsi_pll_10nm_destroy,

		.save_state = dsi_pll_10nm_save_state,

		.restore_state = dsi_pll_10nm_restore_state,

		.set_usecase = dsi_pll_10nm_set_usecase,

	},

	.io_start = { 0xc994400, 0xc996400 },

	.num_dsi_phy = 2,

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+32 −15
Original line number Diff line number Diff line
@@ -1042,18 +1042,20 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm) 
	return 0;

}



struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)

static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)

{

	struct platform_device *pdev = phy->pdev;

	int id = phy->id;

	struct dsi_pll_14nm *pll_14nm;

	struct msm_dsi_pll *pll;

	int ret;



	if (!pdev)

		return ERR_PTR(-ENODEV);

		return -ENODEV;



	pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);

	if (!pll_14nm)

		return ERR_PTR(-ENOMEM);

		return -ENOMEM;



	DBG("PLL%d", id);
@@ -1064,13 +1066,13 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) 
	pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");

	if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map CMN PHY base\n");

		return ERR_PTR(-ENOMEM);

		return -ENOMEM;

	}



	pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");

	if (IS_ERR_OR_NULL(pll_14nm->mmio)) {

		DRM_DEV_ERROR(&pdev->dev, "failed to map PLL base\n");

		return ERR_PTR(-ENOMEM);

		return -ENOMEM;

	}



	spin_lock_init(&pll_14nm->postdiv_lock);
@@ -1078,24 +1080,19 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id) 
	pll = &pll_14nm->base;

	pll->min_rate = VCO_MIN_RATE;

	pll->max_rate = VCO_MAX_RATE;

	pll->get_provider = dsi_pll_14nm_get_provider;

	pll->destroy = dsi_pll_14nm_destroy;

	pll->disable_seq = dsi_pll_14nm_disable_seq;

	pll->save_state = dsi_pll_14nm_save_state;

	pll->restore_state = dsi_pll_14nm_restore_state;

	pll->set_usecase = dsi_pll_14nm_set_usecase;

	pll->cfg = phy->cfg;



	pll_14nm->vco_delay = 1;



	pll->enable_seq = dsi_pll_14nm_enable_seq;



	ret = pll_14nm_register(pll_14nm);

	if (ret) {

		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);

		return ERR_PTR(ret);

		return ret;

	}



	return pll;

	phy->pll = pll;



	return 0;

}



static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
@@ -1230,6 +1227,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 
	.ops = {

		.enable = dsi_14nm_phy_enable,

		.disable = dsi_14nm_phy_disable,

		.pll_init = dsi_pll_14nm_init,

	},

	.pll_ops = {

		.get_provider = dsi_pll_14nm_get_provider,

		.destroy = dsi_pll_14nm_destroy,

		.save_state = dsi_pll_14nm_save_state,

		.restore_state = dsi_pll_14nm_restore_state,

		.set_usecase = dsi_pll_14nm_set_usecase,

		.disable_seq = dsi_pll_14nm_disable_seq,

		.enable_seq = dsi_pll_14nm_enable_seq,

	},

	.io_start = { 0x994400, 0x996400 },

	.num_dsi_phy = 2,
@@ -1248,6 +1255,16 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { 
	.ops = {

		.enable = dsi_14nm_phy_enable,

		.disable = dsi_14nm_phy_disable,

		.pll_init = dsi_pll_14nm_init,

	},

	.pll_ops = {

		.get_provider = dsi_pll_14nm_get_provider,

		.destroy = dsi_pll_14nm_destroy,

		.save_state = dsi_pll_14nm_save_state,

		.restore_state = dsi_pll_14nm_restore_state,

		.set_usecase = dsi_pll_14nm_set_usecase,

		.disable_seq = dsi_pll_14nm_disable_seq,

		.enable_seq = dsi_pll_14nm_enable_seq,

	},

	.io_start = { 0xc994400, 0xc996000 },

	.num_dsi_phy = 2,