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Commit 80b4ae7a authored by Scott Wood's avatar Scott Wood Committed by Stephen Boyd
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clk: qoriq: Separate root input clock for core PLLs on ls1012a



ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: default avatarScott Wood <oss@buserror.net>
Signed-off-by: default avatarTang Yuantian <andy.tang@nxp.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 3d362b1f
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