Commit 805ada63 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2022-06-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- General driver clean-up (Jani, Ville, Julia)
- DG2 enabling (Anusha, Vandita)
- Fix sparse warnings (Imre, Jani)
- DMC MMIO range checks (Anusha)
- Audio related fixes (Jani)
- Runtime PM fixes (Anshuman)
- PSR fixes (Jouni, Jose)
- Media freq factor and per-gt enhancements (Ashutosh, Dale)
- DSI fixes for ICL+ (Jani)
- Disable DMC flip queue handlers (Imre)
- ADL_P voltage swing updates (Balasubramani)
- Use more the VBT for panel information (Ville, Animesh)
- Fix on Type-C ports with TBT mode (Vivek)
- Improve fastset and allow seamless M/N changes (Ville)
- Accept more fixed modes with VRR/DMRRS panels (Ville)
- FBC fix (Jose)
- Remove noise logs (Luca)
- Disable connector polling for a headless SKU (Jouni)
- Sanitize display underrun reporting (Ville)
- ADL-S display PLL w/a (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YrNzP2WTf3WBvpvd@intel.com
parents 0936de1e 6434cf63

drivers/gpu/drm/i915/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -220,6 +220,7 @@ i915-y += \ 
	display/intel_combo_phy.o \

	display/intel_connector.o \

	display/intel_crtc.o \

	display/intel_crtc_state_dump.o \

	display/intel_cursor.o \

	display/intel_display.o \

	display/intel_display_power.o \
@@ -242,6 +243,8 @@ i915-y += \ 
	display/intel_hdcp.o \

	display/intel_hotplug.o \

	display/intel_lpe_audio.o \

	display/intel_modeset_verify.o \

	display/intel_modeset_setup.o \

	display/intel_overlay.o \

	display/intel_pch_display.o \

	display/intel_pch_refclk.o \

drivers/gpu/drm/i915/TODO.txt

+1 −1
Original line number Diff line number Diff line
@@ -37,5 +37,5 @@ Smaller things: 


  https://lore.kernel.org/linux-mm/20210301083320.943079-1-hch@lst.de/



- tasklet helpers in i915_gem.h also look a bit misplaced and should

- tasklet helpers in i915_tasklet.h also look a bit misplaced and should

  probably be moved to tasklet headers.

drivers/gpu/drm/i915/display/g4x_dp.c

+2 −20
Original line number Diff line number Diff line
@@ -395,26 +395,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
		intel_dotclock_calculate(pipe_config->port_clock,

					 &pipe_config->dp_m_n);



	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&

	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {

		/*

		 * This is a big fat ugly hack.

		 *

		 * Some machines in UEFI boot mode provide us a VBT that has 18

		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons

		 * unknown we fail to light up. Yet the same BIOS boots up with

		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as

		 * max, not what it tells us to use.

		 *

		 * Note: This will still be broken if the eDP panel is not lit

		 * up by the BIOS, and thus we can't get the mode at module

		 * load.

		 */

		drm_dbg_kms(&dev_priv->drm,

			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",

			    pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);

		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;

	}

	if (intel_dp_is_edp(intel_dp))

		intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);

}



static void

drivers/gpu/drm/i915/display/hsw_ips.c

+2 −2
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 


	if (IS_BROADWELL(i915)) {

		drm_WARN_ON(&i915->drm,

			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL,

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,

					    IPS_ENABLE | IPS_PCODE_CONTROL));

		/*

		 * Quoting Art Runyan: "its not safe to expect any particular
@@ -62,7 +62,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) 


	if (IS_BROADWELL(i915)) {

		drm_WARN_ON(&i915->drm,

			    snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));

		/*

		 * Wait for PCODE to finish disabling IPS. The BSpec specified

		 * 42ms timeout value leads to occasional timeouts so use 100ms

drivers/gpu/drm/i915/display/icl_dsi.c

+7 −4
Original line number Diff line number Diff line
@@ -1862,7 +1862,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 
{

	struct drm_device *dev = intel_dsi->base.base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;

	struct intel_connector *connector = intel_dsi->attached_connector;

	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;

	u32 tlpx_ns;

	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;

	u32 ths_prepare_ns, tclk_trail_ns;
@@ -2049,6 +2050,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	/* attach connector to encoder */

	intel_connector_attach_encoder(intel_connector, encoder);



	intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);



	mutex_lock(&dev->mode_config.mutex);

	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);

	mutex_unlock(&dev->mode_config.mutex);
@@ -2062,13 +2065,13 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 


	intel_backlight_setup(intel_connector, INVALID_PIPE);



	if (dev_priv->vbt.dsi.config->dual_link)

	if (intel_connector->panel.vbt.dsi.config->dual_link)

		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);

	else

		intel_dsi->ports = BIT(port);



	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;

	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;

	intel_dsi->dcs_backlight_ports = intel_connector->panel.vbt.dsi.bl_ports;

	intel_dsi->dcs_cabc_ports = intel_connector->panel.vbt.dsi.cabc_ports;



	for_each_dsi_port(port, intel_dsi->ports) {

		struct intel_dsi_host *host;