Commit 0936de1e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-misc-next-2022-06-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 



drm-misc-next for v5.20:

UAPI Changes:

 * media: Add various RGB666 and RGB888 format constants

Cross-subsystem Changes:

 * media: Documentation

Core Changes:

 * aperture: Fix segfault during hot-unplug

 * dp: Support waiting for HDP signal, plus driver updates;
   Port-validation fixes

 * fbcon: Improve scrolling performance; Sanitize input

 * Clean up <drm/drm_crtc.h>

Driver Changes:

 * amdgpu: Cleanups

 * bridge: Add support for i.MX8qxp and i.MX8qm; anx7625: DPI fixes;
   tc358775: Fix clock settings; ti-sn65dsi83: Allow GPIO to sleep

 * panel: Set orientation from panel, plus driver updates

 * Several small cleanups

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/YrQeAAVvQ6jxu2dl@linux-uq9g
parents 0a2af0bd 009a3a52

Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml

+18 −1
Original line number Original line Diff line number Diff line
@@ -94,7 +94,22 @@ properties: 
        $ref: /schemas/graph.yaml#/$defs/port-base

        $ref: /schemas/graph.yaml#/$defs/port-base

        unevaluatedProperties: false

        unevaluatedProperties: false

        description:

        description:

          Video port for MIPI DSI input.

          MIPI DSI/DPI input.



        properties:

          endpoint:

            $ref: /schemas/media/video-interfaces.yaml#

            type: object

            additionalProperties: false



            properties:

              remote-endpoint: true



              bus-type:

                enum: [7]

                default: 1



              data-lanes: true





      port@1:

      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        $ref: /schemas/graph.yaml#/properties/port
@@ -143,6 +158,8 @@ examples: 
                    reg = <0>;

                    reg = <0>;

                    anx7625_in: endpoint {

                    anx7625_in: endpoint {

                        remote-endpoint = <&mipi_dsi>;

                        remote-endpoint = <&mipi_dsi>;

                        bus-type = <7>;

                        data-lanes = <0 1 2 3>;

                    };

                    };

                };

                };

Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8qm/qxp LVDS Display Bridge



maintainers:

  - Liu Ying <victor.liu@nxp.com>



description: |

  The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.



  The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.

  The CSR module, as a system controller, contains the LDB's configuration

  registers.



  For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color

  format and can map the input to VESA or JEIDA standards.  The two channels

  cannot be used simultaneously, that is to say, the user should pick one of

  them to use.  Two LDB channels from two LDB instances can work together in

  LDB split mode to support a dual link LVDS display.  The channel indexes

  have to be different.  Channel0 outputs odd pixels and channel1 outputs

  even pixels.



  For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel

  input color format.  The two channels can be used simultaneously, either

  in dual mode or split mode.  In dual mode, the two channels output identical

  data.  In split mode, channel0 outputs odd pixels and channel1 outputs even

  pixels.



  A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in

  the SoC reference manuals.  The pixel mapper uses logic of LDBs embedded in

  i.MX6qdl/sx SoCs, i.e., it is essentially based on them.  To keep the naming

  consistency, this binding calls it LDB.



properties:

  compatible:

    enum:

      - fsl,imx8qm-ldb

      - fsl,imx8qxp-ldb



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



  clocks:

    items:

      - description: pixel clock

      - description: bypass clock



  clock-names:

    items:

      - const: pixel

      - const: bypass



  power-domains:

    maxItems: 1



  fsl,companion-ldb:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      A phandle which points to companion LDB which is used in LDB split mode.



patternProperties:

  "^channel@[0-1]$":

    type: object

    description: Represents a channel of LDB.



    properties:

      "#address-cells":

        const: 1



      "#size-cells":

        const: 0



      reg:

        description: The channel index.

        enum: [ 0, 1 ]



      phys:

        description: A phandle to the phy module representing the LVDS PHY.

        maxItems: 1



      phy-names:

        const: lvds_phy



      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Input port of the channel.



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: Output port of the channel.



    required:

      - "#address-cells"

      - "#size-cells"

      - reg

      - phys

      - phy-names



    additionalProperties: false



required:

  - compatible

  - "#address-cells"

  - "#size-cells"

  - clocks

  - clock-names

  - power-domains

  - channel@0

  - channel@1



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qm-ldb

    then:

      properties:

        fsl,companion-ldb: false



additionalProperties: false



examples:

  - |

    #include <dt-bindings/firmware/imx/rsrc.h>

    ldb {

        #address-cells = <1>;

        #size-cells = <0>;

        compatible = "fsl,imx8qxp-ldb";

        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,

                 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;

        clock-names = "pixel", "bypass";

        power-domains = <&pd IMX_SC_R_LVDS_0>;



        channel@0 {

            #address-cells = <1>;

            #size-cells = <0>;

            reg = <0>;

            phys = <&mipi_lvds_0_phy>;

            phy-names = "lvds_phy";



            port@0 {

                reg = <0>;



                mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {

                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;

                };

            };

        };



        channel@1 {

            #address-cells = <1>;

            #size-cells = <0>;

            reg = <1>;

            phys = <&mipi_lvds_0_phy>;

            phy-names = "lvds_phy";



            port@0 {

                reg = <0>;



                mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {

                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;

                };

            };

        };

    };

Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8qm/qxp Pixel Combiner



maintainers:

  - Liu Ying <victor.liu@nxp.com>



description: |

  The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a

  single display controller and manipulates the two streams to support a number

  of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as

  either one screen, two screens, or virtual screens.  The pixel combiner is

  also responsible for generating some of the control signals for the pixel link

  output channel.



properties:

  compatible:

    enum:

      - fsl,imx8qm-pixel-combiner

      - fsl,imx8qxp-pixel-combiner



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: apb



  power-domains:

    maxItems: 1



patternProperties:

  "^channel@[0-1]$":

    type: object

    description: Represents a display stream of pixel combiner.



    properties:

      "#address-cells":

        const: 1



      "#size-cells":

        const: 0



      reg:

        description: The display stream index.

        enum: [ 0, 1 ]



      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Input endpoint of the display stream.



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: Output endpoint of the display stream.



    required:

      - "#address-cells"

      - "#size-cells"

      - reg

      - port@0

      - port@1



    additionalProperties: false



required:

  - compatible

  - "#address-cells"

  - "#size-cells"

  - reg

  - clocks

  - clock-names

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>

    pixel-combiner@56020000 {

        compatible = "fsl,imx8qxp-pixel-combiner";

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <0x56020000 0x10000>;

        clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;

        clock-names = "apb";

        power-domains = <&pd IMX_SC_R_DC_0>;



        channel@0 {

            #address-cells = <1>;

            #size-cells = <0>;

            reg = <0>;



            port@0 {

                reg = <0>;



                dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {

                    remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;

                };

            };



            port@1 {

                reg = <1>;



                dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {

                    remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;

                };

            };

        };



        channel@1 {

            #address-cells = <1>;

            #size-cells = <0>;

            reg = <1>;



            port@0 {

                reg = <0>;



                dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {

                    remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;

                };

            };



            port@1 {

                reg = <1>;



                dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {

                    remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;

                };

            };

        };

    };

Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8qm/qxp Display Pixel Link



maintainers:

  - Liu Ying <victor.liu@nxp.com>



description: |

  The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard

  asynchronous linkage between pixel sources(display controller or

  camera module) and pixel consumers(imaging or displays).

  It consists of two distinct functions, a pixel transfer function and a

  control interface.  Multiple pixel channels can exist per one control channel.

  This binding documentation is only for pixel links whose pixel sources are

  display controllers.



  The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)

  firmware.



properties:

  compatible:

    enum:

      - fsl,imx8qm-dc-pixel-link

      - fsl,imx8qxp-dc-pixel-link



  fsl,dc-id:

    $ref: /schemas/types.yaml#/definitions/uint8

    description: |

      u8 value representing the display controller index that the pixel link

      connects to.



  fsl,dc-stream-id:

    $ref: /schemas/types.yaml#/definitions/uint8

    description: |

      u8 value representing the display controller stream index that the pixel

      link connects to.

    enum: [0, 1]



  ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: The pixel link input port node from upstream video source.



    patternProperties:

      "^port@[1-4]$":

        $ref: /schemas/graph.yaml#/properties/port

        description: The pixel link output port node to downstream bridge.



    required:

      - port@0

      - port@1

      - port@2

      - port@3

      - port@4



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qxp-dc-pixel-link

    then:

      properties:

        fsl,dc-id:

          const: 0



  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qm-dc-pixel-link

    then:

      properties:

        fsl,dc-id:

          enum: [0, 1]



required:

  - compatible

  - fsl,dc-id

  - fsl,dc-stream-id

  - ports



additionalProperties: false



examples:

  - |

    dc0-pixel-link0 {

        compatible = "fsl,imx8qxp-dc-pixel-link";

        fsl,dc-id = /bits/ 8 <0>;

        fsl,dc-stream-id = /bits/ 8 <0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            /* from dc0 pixel combiner channel0 */

            port@0 {

                reg = <0>;



                dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {

                    remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;

                };

            };



            /* to PXL2DPIs in MIPI/LVDS combo subsystems */

            port@1 {

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <1>;



                dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {

                    reg = <0>;

                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;

                };



                dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {

                    reg = <1>;

                    remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;

                };

            };



            /* unused */

            port@2 {

                reg = <2>;

            };



            /* unused */

            port@3 {

                reg = <3>;

            };



            /* to imaging subsystem */

            port@4 {

                reg = <4>;

            };

        };

    };

Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface



maintainers:

  - Liu Ying <victor.liu@nxp.com>



description: |

  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)

  interfaces the pixel link 36-bit data output and the DSI controller’s

  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module

  used in LVDS mode, to remap the pixel color codings between those modules.

  This module is purely combinatorial.



  The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.

  The CSR module, as a system controller, contains the PXL2DPI's configuration

  register.



properties:

  compatible:

    const: fsl,imx8qxp-pxl2dpi



  fsl,sc-resource:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: The SCU resource ID associated with this PXL2DPI instance.



  power-domains:

    maxItems: 1



  fsl,companion-pxl2dpi:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      A phandle which points to companion PXL2DPI which is used by downstream

      LVDS Display Bridge(LDB) in split mode.



  ports:

    $ref: /schemas/graph.yaml#/properties/ports



    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: The PXL2DPI input port node from pixel link.



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: The PXL2DPI output port node to downstream bridge.



    required:

      - port@0

      - port@1



required:

  - compatible

  - fsl,sc-resource

  - power-domains

  - ports



additionalProperties: false



examples:

  - |

    #include <dt-bindings/firmware/imx/rsrc.h>

    pxl2dpi {

        compatible = "fsl,imx8qxp-pxl2dpi";

        fsl,sc-resource = <IMX_SC_R_MIPI_0>;

        power-domains = <&pd IMX_SC_R_MIPI_0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <0>;



                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {

                    reg = <0>;

                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;

                };



                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {

                     reg = <1>;

                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;

                };

            };



            port@1 {

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <1>;



                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {

                    reg = <0>;

                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;

                };



                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {

                    reg = <1>;

                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;

                };

            };

        };

    };