Commit 7fc5c319 authored by Paul Hsieh's avatar Paul Hsieh Committed by Alex Deucher
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drm/amd/display: dmcu wait loop calculation is incorrect in RV 



[Why]
Driver already get display clock from SMU base on MHz, but driver read
again and mutiple 1000 cause wait loop value is overflow.

[How]
remove coding error

Signed-off-by: default avatarPaul Hsieh <paul.hsieh@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 904fb6e0

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

+0 −3
Original line number Diff line number Diff line
@@ -97,9 +97,6 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_di 
			VBIOSSMC_MSG_SetDispclkFreq,

			requested_dispclk_khz / 1000);



	/* Actual dispclk set is returned in the parameter register */

	actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;



	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)