iommu/vt-d: Disable SVM when ATS/PRI/PASID are not enabled in the device

mainline inclusion
from mainline-v5.13
commit dec991e4
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I596WO


CVE: NA

Intel-SIG: commit dec991e4 iommu/vt-d: Disable SVM when ATS/PRI/PASID are not enabled in the device.
Incremental backporting patches for DSA/IAA on Intel Xeon platform.

--------------------------------

Currently, the Intel VT-d supports Shared Virtual Memory (SVM) only when
IO page fault is supported. Otherwise, shared memory pages can not be
swapped out and need to be pinned. The device needs the Address Translation
Service (ATS), Page Request Interface (PRI) and Process Address Space
Identifier (PASID) capabilities to be enabled to support IO page fault.

Disable SVM when ATS, PRI and PASID are not enabled in the device.

Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210314201534.918-1-kyung.min.park@intel.com


Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>