Commit 7e724422 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v5.20' of... 

Merge tag 'coresight-next-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-next

Suzuki writes:

CoreSight self-hosted tracing changes for v5.20.

 - Fixes LOCKDEP warnings on module unload with configfs
 - Conversion of DT bindings to DT schema
 - Branch broadcast support for perf cs_etm
 - Etm4x driver fixes for build failures with Clang and unrolled loops

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>

* tag 'coresight-next-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux:
  coresight: etm4x: avoid build failure with unrolled loops
  Documentation: coresight: Expand branch broadcast documentation
  Documentation: coresight: Link config options to existing documentation
  Documentation: coresight: Turn numbered subsections into real subsections
  coresight: Add config flag to enable branch broadcast
  Documentation: coresight: Escape coresight bindings file wildcard
  dt-bindings: arm: Convert CoreSight CPU debug to DT schema
  dt-bindings: arm: Convert CoreSight bindings to DT schema
  dt-bindings: arm: Rename Coresight filenames to match compatible
  coresight: syscfg: Update load and unload operations
  coresight: configfs: Fix unload of configurations on module exit
  coresight: Clear the connection field properly
parents 4682f213 4d45bc82

Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Arm Coresight Address Translation Unit (CATU)



maintainers:

  - Mathieu Poirier <mathieu.poirier@linaro.org>

  - Mike Leach <mike.leach@linaro.org>

  - Leo Yan <leo.yan@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>



description: |

  CoreSight components are compliant with the ARM CoreSight architecture

  specification and can be connected in various topologies to suit a particular

  SoCs tracing needs. These trace components can generally be classified as

  sinks, links and sources. Trace data produced by one or more sources flows

  through the intermediate links connecting the source to the currently selected

  sink.



  The CoreSight Address Translation Unit (CATU) translates addresses between an

  AXI master and system memory. The CATU is normally used along with the TMC to

  implement scattering of virtual trace buffers in physical memory. The CATU

  translates contiguous Virtual Addresses (VAs) from an AXI master into

  non-contiguous Physical Addresses (PAs) that are intended for system memory.



# Need a custom select here or 'arm,primecell' will match on lots of nodes

select:

  properties:

    compatible:

      contains:

        const: arm,coresight-catu

  required:

    - compatible



allOf:

  - $ref: /schemas/arm/primecell.yaml#



properties:

  compatible:

    items:

      - const: arm,coresight-catu

      - const: arm,primecell



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    items:

      - const: apb_pclk

      - const: atclk



  interrupts:

    maxItems: 1

    description: Address translation error interrupt



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports

    additionalProperties: false



    properties:

      port:

        description: AXI Slave connected to another Coresight component

        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - in-ports



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    catu@207e0000 {

        compatible = "arm,coresight-catu", "arm,primecell";

        reg = <0x207e0000 0x1000>;



        clocks = <&oscclk6a>;

        clock-names = "apb_pclk";



        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

        in-ports {

            port {

                catu_in_port: endpoint {

                    remote-endpoint = <&etr_out_port>;

                };

            };

        };

    };

...

Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: CoreSight CPU Debug Component



maintainers:

  - Mathieu Poirier <mathieu.poirier@linaro.org>

  - Mike Leach <mike.leach@linaro.org>

  - Leo Yan <leo.yan@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>



description: |

  CoreSight CPU debug component are compliant with the ARMv8 architecture

  reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The

  external debug module is mainly used for two modes: self-hosted debug and

  external debug, and it can be accessed from mmio region from Coresight and

  eventually the debug module connects with CPU for debugging. And the debug

  module provides sample-based profiling extension, which can be used to sample

  CPU program counter, secure state and exception level, etc; usually every CPU

  has one dedicated debug module to be connected.



select:

  properties:

    compatible:

      contains:

        const: arm,coresight-cpu-debug

  required:

    - compatible



allOf:

  - $ref: /schemas/arm/primecell.yaml#



properties:

  compatible:

    items:

      - const: arm,coresight-cpu-debug

      - const: arm,primecell



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    maxItems: 1



  cpu:

    description:

      A phandle to the cpu this debug component is bound to.

    $ref: /schemas/types.yaml#/definitions/phandle



  power-domains:

    maxItems: 1

    description:

      A phandle to the debug power domain if the debug logic has its own

      dedicated power domain. CPU idle states may also need to be separately

      constrained to keep CPU cores powered.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - cpu



unevaluatedProperties: false



examples:

  - |

    debug@f6590000 {

        compatible = "arm,coresight-cpu-debug", "arm,primecell";

        reg = <0xf6590000 0x1000>;

        clocks = <&sys_ctrl 1>;

        clock-names = "apb_pclk";

        cpu = <&cpu0>;

    };

...

Documentation/devicetree/bindings/arm/coresight-cti.yaml→Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml

+2 −3
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@@ -2,7 +2,7 @@ 
# Copyright 2019 Linaro Ltd.

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#

$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Coresight Cross Trigger Interface (CTI) device.
@@ -12,8 +12,7 @@ description: | 
  to one or more CoreSight components and/or a CPU, with CTIs interconnected in

  a star topology via the Cross Trigger Matrix (CTM), which is not programmable.

  The ECT components are not part of the trace generation data path and are thus

  not part of the CoreSight graph described in the general CoreSight bindings

  file coresight.txt.

  not part of the CoreSight graph.



  The CTI component properties define the connections between the individual

  CTI and the components it is directly connected to, consisting of input and

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Arm CoreSight Programmable Trace Bus Funnel



maintainers:

  - Mathieu Poirier <mathieu.poirier@linaro.org>

  - Mike Leach <mike.leach@linaro.org>

  - Leo Yan <leo.yan@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>



description: |

  CoreSight components are compliant with the ARM CoreSight architecture

  specification and can be connected in various topologies to suit a particular

  SoCs tracing needs. These trace components can generally be classified as

  sinks, links and sources. Trace data produced by one or more sources flows

  through the intermediate links connecting the source to the currently selected

  sink.



  The Coresight funnel merges 2-8 trace sources into a single trace

  stream with programmable enable and priority of input ports.



# Need a custom select here or 'arm,primecell' will match on lots of nodes

select:

  properties:

    compatible:

      contains:

        const: arm,coresight-dynamic-funnel

  required:

    - compatible



allOf:

  - $ref: /schemas/arm/primecell.yaml#



properties:

  compatible:

    items:

      - const: arm,coresight-dynamic-funnel

      - const: arm,primecell



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    items:

      - const: apb_pclk

      - const: atclk



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports



    patternProperties:

      '^port(@[0-7])?$':

        description: Input connections from CoreSight Trace bus

        $ref: /schemas/graph.yaml#/properties/port



  out-ports:

    $ref: /schemas/graph.yaml#/properties/ports

    additionalProperties: false



    properties:

      port:

        description: Output connection to CoreSight Trace bus

        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - in-ports

  - out-ports



unevaluatedProperties: false



examples:

  - |

    funnel@20040000 {

        compatible = "arm,coresight-dynamic-funnel", "arm,primecell";

        reg = <0x20040000 0x1000>;



        clocks = <&oscclk6a>;

        clock-names = "apb_pclk";

        out-ports {

            port {

                funnel_out_port0: endpoint {

                    remote-endpoint = <&replicator_in_port0>;

                };

            };

        };



        in-ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                funnel_in_port0: endpoint {

                    remote-endpoint = <&ptm0_out_port>;

                };

            };



            port@1 {

                reg = <1>;

                funnel_in_port1: endpoint {

                    remote-endpoint = <&ptm1_out_port>;

                };

            };



            port@2 {

                reg = <2>;

                funnel_in_port2: endpoint {

                    remote-endpoint = <&etm0_out_port>;

                };

            };

        };

    };

...

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Arm Coresight Programmable Trace Bus Replicator



maintainers:

  - Mathieu Poirier <mathieu.poirier@linaro.org>

  - Mike Leach <mike.leach@linaro.org>

  - Leo Yan <leo.yan@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>



description: |

  CoreSight components are compliant with the ARM CoreSight architecture

  specification and can be connected in various topologies to suit a particular

  SoCs tracing needs. These trace components can generally be classified as

  sinks, links and sources. Trace data produced by one or more sources flows

  through the intermediate links connecting the source to the currently selected

  sink.



  The Coresight replicator splits a single trace stream into two trace streams

  for systems that have more than one trace sink component.



# Need a custom select here or 'arm,primecell' will match on lots of nodes

select:

  properties:

    compatible:

      contains:

        const: arm,coresight-dynamic-replicator

  required:

    - compatible



allOf:

  - $ref: /schemas/arm/primecell.yaml#



properties:

  compatible:

    items:

      - const: arm,coresight-dynamic-replicator

      - const: arm,primecell



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    items:

      - const: apb_pclk

      - const: atclk



  qcom,replicator-loses-context:

    type: boolean

    description:

      Indicates that the replicator will lose register context when AMBA clock

      is removed which is observed in some replicator designs.



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports

    additionalProperties: false



    properties:

      port:

        description: Input connection from CoreSight Trace bus

        $ref: /schemas/graph.yaml#/properties/port



  out-ports:

    $ref: /schemas/graph.yaml#/properties/ports



    patternProperties:

      '^port(@[01])?$':

        description: Output connections to CoreSight Trace bus

        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - in-ports

  - out-ports



unevaluatedProperties: false



examples:

  - |

    replicator@20120000 {

        compatible = "arm,coresight-dynamic-replicator", "arm,primecell";

        reg = <0x20120000 0x1000>;



        clocks = <&soc_smc50mhz>;

        clock-names = "apb_pclk";



        out-ports {

            #address-cells = <1>;

            #size-cells = <0>;



            /* replicator output ports */

            port@0 {

                reg = <0>;

                replicator_out_port0: endpoint {

                    remote-endpoint = <&tpiu_in_port>;

                };

            };



            port@1 {

                reg = <1>;

                replicator_out_port1: endpoint {

                    remote-endpoint = <&etr_in_port>;

                };

            };

        };

        in-ports {

            port {

                replicator_in_port0: endpoint {

                    remote-endpoint = <&csys2_funnel_out_port>;

                };

            };

        };

    };

...