Commit 4682f213 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'fpga-late-for-5.20-rc1' of... 

Merge tag 'fpga-late-for-5.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga

 into char-misc-next

Xu writes:

Here is the second set of FPGA changes for 5.20-rc1

FPGA Manager core:
- Ivan's change to support image offset and data size setting for
reprograming. A parse_header() callback is introduced for drivers to
specify these info.
- Colin's immediate spelling fix for Ivan's patch.

Microchip:
- Ivan's change to add Microchip MPF FPGA manager driver. And MAINTAINERS
entry added for the driver.

All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).

Signed-off-by: default avatarXu Yilun <yilun.xu@intel.com>

* tag 'fpga-late-for-5.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
  fpga: fpga-mgr: Fix spelling mistake "bitsream" -> "bitstream"
  MAINTAINERS: add Microchip PolarFire FPGA drivers entry
  dt-bindings: fpga: add binding doc for microchip-spi fpga mgr
  fpga: microchip-spi: add Microchip MPF FPGA manager
  docs: fpga: mgr: document parse_header() callback
  fpga: fpga-mgr: support bitstream offset in image buffer
parents f5fd903b ee794221

Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip Polarfire FPGA manager.



maintainers:

  - Ivan Bornyakov <i.bornyakov@metrotek.ru>



description:

  Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to

  load the bitstream in .dat format.



properties:

  compatible:

    enum:

      - microchip,mpf-spi-fpga-mgr



  reg:

    description: SPI chip select

    maxItems: 1



  spi-max-frequency: true



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    spi {

            #address-cells = <1>;

            #size-cells = <0>;



            fpga_mgr@0 {

                    compatible = "microchip,mpf-spi-fpga-mgr";

                    spi-max-frequency = <20000000>;

                    reg = <0>;

            };

    };

Documentation/driver-api/fpga/fpga-mgr.rst

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@@ -79,12 +79,27 @@ do the programming sequence for this particular FPGA. These ops return 0 for 
success or negative error codes otherwise.



The programming sequence is::

 1. .write_init

 2. .write or .write_sg (may be called once or multiple times)

 3. .write_complete

 1. .parse_header (optional, may be called once or multiple times)

 2. .write_init

 3. .write or .write_sg (may be called once or multiple times)

 4. .write_complete



The .parse_header function will set header_size and data_size to

struct fpga_image_info. Before parse_header call, header_size is initialized

with initial_header_size. If flag skip_header of fpga_manager_ops is true,

.write function will get image buffer starting at header_size offset from the

beginning. If data_size is set, .write function will get data_size bytes of

the image buffer, otherwise .write will get data up to the end of image buffer.

This will not affect .write_sg, .write_sg will still get whole image in

sg_table form. If FPGA image is already mapped as a single contiguous buffer,

whole buffer will be passed into .parse_header. If image is in scatter-gather

form, core code will buffer up at least .initial_header_size before the first

call of .parse_header, if it is not enough, .parse_header should set desired

size into info->header_size and return -EAGAIN, then it will be called again

with greater part of image buffer on the input.



The .write_init function will prepare the FPGA to receive the image data. The

buffer passed into .write_init will be at most .initial_header_size bytes long;

buffer passed into .write_init will be at least info->header_size bytes long;

if the whole bitstream is not immediately available then the core code will

buffer up at least this much before starting.

MAINTAINERS

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@@ -7914,6 +7914,14 @@ S: Maintained 
F:	Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update

F:	drivers/fpga/intel-m10-bmc-sec-update.c









MICROCHIP POLARFIRE FPGA DRIVERS









M:	Conor Dooley <conor.dooley@microchip.com>









R:	Ivan Bornyakov <i.bornyakov@metrotek.ru>









L:	linux-fpga@vger.kernel.org









S:	Supported









F:	Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml









F:	drivers/fpga/microchip-spi.c

















FPU EMULATOR









M:	Bill Metzenthen <billm@melbpc.org.au>









S:	Maintained
































drivers/fpga/Kconfig



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@@ -255,4 +255,12 @@ config FPGA_M10_BMC_SEC_UPDATE







	  (BMC) and provides support for secure updates for the BMC image,









	  the FPGA image, the Root Entry Hashes, etc.



















config FPGA_MGR_MICROCHIP_SPI









	tristate "Microchip Polarfire SPI FPGA manager"









	depends on SPI









	help









	  FPGA manager driver support for Microchip Polarfire FPGAs









	  programming over slave SPI interface with .dat formatted









	  bitstream image.



















endif # FPGA
























drivers/fpga/Makefile



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@@ -19,6 +19,7 @@ obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o







obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o









obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o









obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)	+= versal-fpga.o









obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI)	+= microchip-spi.o









obj-$(CONFIG_ALTERA_PR_IP_CORE)		+= altera-pr-ip-core.o









obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)	+= altera-pr-ip-core-plat.o