Commit 7db581d6 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: allow windowed mpo + odm 



This change adds a config flag to allow non fullscreen MPO during ODM.
Scaling calculation will still fail configurations where video is only
one one side of the screen.

Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: default avatarAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b8f02088

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+11 −3
Original line number Diff line number Diff line
@@ -1155,9 +1155,17 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 
			pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;

	}



	if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {

		if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||

				pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)

			res = false;

	} else {

		/* Clamp minimum viewport size */

		if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)

			pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;

		if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)

			pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;

	}



	DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"

			"src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -323,6 +323,7 @@ struct dc_config { 
	bool multi_mon_pp_mclk_switch;

	bool disable_dmcu;

	bool enable_4to1MPC;

	bool enable_windowed_mpo_odm;

	bool allow_edp_hotplug_detection;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	bool clamp_min_dcfclk;

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+16 −14
Original line number Diff line number Diff line
@@ -1929,6 +1929,7 @@ noinline bool dcn30_internal_validate_bw( 
	if (vlevel == context->bw_ctx.dml.soc.num_states)

		goto validate_fail;



	if (!dc->config.enable_windowed_mpo_odm) {

		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

			struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
@@ -1947,6 +1948,7 @@ noinline bool dcn30_internal_validate_bw( 
			}

			pipe_idx++;

		}

	}



	/* merge pipes if necessary */

	for (i = 0; i < dc->res_pool->pipe_count; i++) {