Commit 7a557521 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa 

Pull xtensa updates from Max Filippov:

 - implement atomic operations using exclusive access Xtensa option
   operations

 - add support for Xtensa cores with memory protection unit (MPU)

 - clean up xtensa-specific kernel-only headers

 - fix error path in simdisk_setup

* tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa:
  xtensa: implement initialize_cacheattr for MPU cores
  xtensa: add exclusive atomics support
  xtensa: clean up inline assembly in futex.h
  xtensa: replace variant/core.h with asm/core.h
  xtensa: drop ifdef __KERNEL__ from kernel-only headers
  xtensa: set proper error code for simdisk_setup()
  xtensa: fix incorrect fd close in error case of simdisk_setup()
parents 1fb3b526 a5944195

arch/xtensa/Kconfig

+20 −6
Original line number Diff line number Diff line
@@ -253,12 +253,26 @@ config MEMMAP_CACHEATTR 
	  region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,

	  bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.



	  Cache attribute values are specific for the MMU type, so e.g.

	  for region protection MMUs: 2 is cache bypass, 4 is WB cached,

	  1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,

	  bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,

	  1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is

	  reserved).

	  Cache attribute values are specific for the MMU type.

	  For region protection MMUs:

	    1: WT cached,

	    2: cache bypass,

	    4: WB cached,

	    f: illegal.

	  For ful MMU:

	    bit 0: executable,

	    bit 1: writable,

	    bits 2..3:

	      0: cache bypass,

	      1: WB cache,

	      2: WT cache,

	      3: special (c and e are illegal, f is reserved).

	  For MPU:

	    0: illegal,

	    1: WB cache,

	    2: WB, no-write-allocate cache,

	    3: WT cache,

	    4: cache bypass.



config KSEG_PADDR

	hex "Physical address of the KSEG mapping"

arch/xtensa/boot/boot-redboot/bootstrap.S

+1 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#include <variant/core.h>

#include <asm/core.h>

#include <asm/regs.h>

#include <asm/asmmacro.h>

#include <asm/cacheasm.h>

arch/xtensa/include/asm/asmmacro.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#ifndef _XTENSA_ASMMACRO_H

#define _XTENSA_ASMMACRO_H



#include <variant/core.h>

#include <asm/core.h>



/*

 * Some little helpers for loops. Use zero-overhead-loops

arch/xtensa/include/asm/atomic.h

+61 −5
Original line number Diff line number Diff line
@@ -15,8 +15,6 @@ 


#include <linux/stringify.h>

#include <linux/types.h>



#ifdef __KERNEL__

#include <asm/processor.h>

#include <asm/cmpxchg.h>

#include <asm/barrier.h>
@@ -58,7 +56,67 @@ 
 */

#define atomic_set(v,i)		WRITE_ONCE((v)->counter, (i))



#if XCHAL_HAVE_S32C1I

#if XCHAL_HAVE_EXCLUSIVE

#define ATOMIC_OP(op)							\

static inline void atomic_##op(int i, atomic_t *v)			\

{									\

	unsigned long tmp;						\

	int result;							\

									\

	__asm__ __volatile__(						\

			"1:     l32ex   %1, %3\n"			\

			"       " #op " %0, %1, %2\n"			\

			"       s32ex   %0, %3\n"			\

			"       getex   %0\n"				\

			"       beqz    %0, 1b\n"			\

			: "=&a" (result), "=&a" (tmp)			\

			: "a" (i), "a" (v)				\

			: "memory"					\

			);						\

}									\



#define ATOMIC_OP_RETURN(op)						\

static inline int atomic_##op##_return(int i, atomic_t *v)		\

{									\

	unsigned long tmp;						\

	int result;							\

									\

	__asm__ __volatile__(						\

			"1:     l32ex   %1, %3\n"			\

			"       " #op " %0, %1, %2\n"			\

			"       s32ex   %0, %3\n"			\

			"       getex   %0\n"				\

			"       beqz    %0, 1b\n"			\

			"       " #op " %0, %1, %2\n"			\

			: "=&a" (result), "=&a" (tmp)			\

			: "a" (i), "a" (v)				\

			: "memory"					\

			);						\

									\

	return result;							\

}



#define ATOMIC_FETCH_OP(op)						\

static inline int atomic_fetch_##op(int i, atomic_t *v)			\

{									\

	unsigned long tmp;						\

	int result;							\

									\

	__asm__ __volatile__(						\

			"1:     l32ex   %1, %3\n"			\

			"       " #op " %0, %1, %2\n"			\

			"       s32ex   %0, %3\n"			\

			"       getex   %0\n"				\

			"       beqz    %0, 1b\n"			\

			: "=&a" (result), "=&a" (tmp)			\

			: "a" (i), "a" (v)				\

			: "memory"					\

			);						\

									\

	return tmp;							\

}



#elif XCHAL_HAVE_S32C1I

#define ATOMIC_OP(op)							\

static inline void atomic_##op(int i, atomic_t * v)			\

{									\
@@ -200,6 +258,4 @@ ATOMIC_OPS(xor) 
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))



#endif /* __KERNEL__ */



#endif /* _XTENSA_ATOMIC_H */

arch/xtensa/include/asm/barrier.h

+4 −0
Original line number Diff line number Diff line
@@ -9,12 +9,16 @@ 
#ifndef _XTENSA_SYSTEM_H

#define _XTENSA_SYSTEM_H



#include <asm/core.h>



#define mb()  ({ __asm__ __volatile__("memw" : : : "memory"); })

#define rmb() barrier()

#define wmb() mb()



#if XCHAL_HAVE_S32C1I

#define __smp_mb__before_atomic()		barrier()

#define __smp_mb__after_atomic()		barrier()

#endif



#include <asm-generic/barrier.h>