Commit a5944195 authored by Max Filippov's avatar Max Filippov
Browse files

xtensa: implement initialize_cacheattr for MPU cores 



Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent f7c34874

arch/xtensa/Kconfig

+20 −6
Original line number Diff line number Diff line
@@ -256,12 +256,26 @@ config MEMMAP_CACHEATTR 
	  region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,

	  bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.



	  Cache attribute values are specific for the MMU type, so e.g.

	  for region protection MMUs: 2 is cache bypass, 4 is WB cached,

	  1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,

	  bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,

	  1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is

	  reserved).

	  Cache attribute values are specific for the MMU type.

	  For region protection MMUs:

	    1: WT cached,

	    2: cache bypass,

	    4: WB cached,

	    f: illegal.

	  For ful MMU:

	    bit 0: executable,

	    bit 1: writable,

	    bits 2..3:

	      0: cache bypass,

	      1: WB cache,

	      2: WT cache,

	      3: special (c and e are illegal, f is reserved).

	  For MPU:

	    0: illegal,

	    1: WB cache,

	    2: WB, no-write-allocate cache,

	    3: WT cache,

	    4: cache bypass.



config KSEG_PADDR

	hex "Physical address of the KSEG mapping"

arch/xtensa/include/asm/core.h

+4 −0
Original line number Diff line number Diff line
@@ -10,6 +10,10 @@ 
#define XCHAL_HAVE_EXCLUSIVE 0

#endif



#ifndef XCHAL_HAVE_MPU

#define XCHAL_HAVE_MPU 0

#endif



#ifndef XCHAL_SPANNING_WAY

#define XCHAL_SPANNING_WAY 0

#endif

arch/xtensa/include/asm/initialize_mmu.h

+33 −1
Original line number Diff line number Diff line
@@ -177,11 +177,42 @@ 


	.macro	initialize_cacheattr



#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS

#if !defined(CONFIG_MMU) && (XCHAL_HAVE_TLBS || XCHAL_HAVE_MPU)

#if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU

#error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU.

#endif



#if XCHAL_HAVE_MPU

	.data

	.align	4

.Lattribute_table:

	.long 0x000000, 0x1fff00, 0x1ddf00, 0x1eef00

	.long 0x006600, 0x000000, 0x000000, 0x000000

	.long 0x000000, 0x000000, 0x000000, 0x000000

	.long 0x000000, 0x000000, 0x000000, 0x000000

	.previous



	movi	a3, .Lattribute_table

	movi	a4, CONFIG_MEMMAP_CACHEATTR

	movi	a5, 1

	movi	a6, XCHAL_MPU_ENTRIES

	movi	a10, 0x20000000

	movi	a11, -1

1:

	sub	a5, a5, a10

	extui	a8, a4, 28, 4

	beq	a8, a11, 2f

	addi	a6, a6, -1

	mov	a11, a8

2:

	addx4	a9, a8, a3

	l32i	a9, a9, 0

	or	a9, a9, a6

	wptlb	a9, a5

	slli	a4, a4, 4

	bgeu	a5, a10, 1b



#else

	movi	a5, XCHAL_SPANNING_WAY

	movi	a6, ~_PAGE_ATTRIB_MASK

	movi	a4, CONFIG_MEMMAP_CACHEATTR
@@ -203,6 +234,7 @@ 
	bgeu	a5, a8, 1b



	isync

#endif

#endif



	.endm