sched,x86: Fix L2 cache mask

mainline inclusion
from mainline-v5.16-rc1
commit 55409ac5
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8LVOX


CVE: N/A

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Intel-SIG: commit 55409ac5 sched,x86: Fix L2 cache mask.
Cluster scheduler feature backport.

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Currently AMD/Hygon do not populate l2c_id, this means that for SMT
enabled systems they report an L2 per thread. This is ofcourse not
true but was harmless so far.

However, since commit: 66558b73 ("sched: Add cluster scheduler
level for x86") the scheduler topology setup requires:

  SMT <= L2 <= LLC

Which leads to noisy warnings and possibly weird behaviour on affected
chips.

Therefore change the topology generation such that if l2c_id is not
populated it follows the SMT topology, thereby satisfying the
constraint.

Fixes: 66558b73 ("sched: Add cluster scheduler level for x86")
Reported-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Aubrey Li <aubrey.li@linux.intel.com>