Commit 78bb1ae5 authored by Alex Bee's avatar Alex Bee Committed by Mauro Carvalho Chehab
Browse files

media: hantro: add support for Rockchip RK3066 



RK3066's VPU IP block is the predecessor from what RK3288 has.
The hardware differences are:
  - supports decoding frame sizes up to 1920x1088 only
  - doesn't have the 'G1_REG_SOFT_RESET' register
    (requires another .reset callback for hantro_codec_ops,
     since writing this register will result in non-working
     IP block)
  - has one ACLK/HCLK per vdpu/vepu
  - ACLKs can be clocked up to 300 MHz only
  - no MMU
    (no changes required: CMA will be transparently used)

Add a new RK3066 variant which reflect this differences. This variant
can be used for RK3188 as well.

Signed-off-by: default avatarAlex Bee <knaerzche@gmail.com>
Reviewed-by: default avatarEzequiel Garcia <ezequiel@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent c9caebd5

drivers/staging/media/hantro/hantro_drv.c

+1 −0
Original line number Diff line number Diff line
@@ -582,6 +582,7 @@ static const struct v4l2_file_operations hantro_fops = { 


static const struct of_device_id of_hantro_match[] = {

#ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP

	{ .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },

	{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },

	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },

	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },

drivers/staging/media/hantro/hantro_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ enum hantro_enc_fmt { 


extern const struct hantro_variant imx8mq_vpu_g2_variant;

extern const struct hantro_variant imx8mq_vpu_variant;

extern const struct hantro_variant rk3066_vpu_variant;

extern const struct hantro_variant rk3288_vpu_variant;

extern const struct hantro_variant rk3328_vpu_variant;

extern const struct hantro_variant rk3399_vpu_variant;

drivers/staging/media/hantro/rockchip_vpu_hw.c

+121 −0
Original line number Diff line number Diff line
@@ -10,9 +10,11 @@ 


#include "hantro.h"

#include "hantro_jpeg.h"

#include "hantro_g1_regs.h"

#include "hantro_h1_regs.h"

#include "rockchip_vpu2_regs.h"



#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)

#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)



/*
@@ -63,6 +65,52 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = { 
	},

};



static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {

	{

		.fourcc = V4L2_PIX_FMT_NV12,

		.codec_mode = HANTRO_MODE_NONE,

	},

	{

		.fourcc = V4L2_PIX_FMT_H264_SLICE,

		.codec_mode = HANTRO_MODE_H264_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 1920,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 1088,

			.step_height = MB_DIM,

		},

	},

	{

		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,

		.codec_mode = HANTRO_MODE_MPEG2_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 1920,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 1088,

			.step_height = MB_DIM,

		},

	},

	{

		.fourcc = V4L2_PIX_FMT_VP8_FRAME,

		.codec_mode = HANTRO_MODE_VP8_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 1920,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 1088,

			.step_height = MB_DIM,

		},

	},

};



static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {

	{

		.fourcc = V4L2_PIX_FMT_NV12,
@@ -196,6 +244,14 @@ static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id) 
	return IRQ_HANDLED;

}



static int rk3066_vpu_hw_init(struct hantro_dev *vpu)

{

	/* Bump ACLKs to max. possible freq. to improve performance. */

	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);

	clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);

	return 0;

}



static int rockchip_vpu_hw_init(struct hantro_dev *vpu)

{

	/* Bump ACLK to max. possible freq. to improve performance. */
@@ -203,6 +259,14 @@ static int rockchip_vpu_hw_init(struct hantro_dev *vpu) 
	return 0;

}



static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;



	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);

	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);

}



static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;
@@ -233,6 +297,33 @@ static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx) 
/*

 * Supported codec ops.

 */

static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {

	[HANTRO_MODE_JPEG_ENC] = {

		.run = hantro_h1_jpeg_enc_run,

		.reset = rockchip_vpu1_enc_reset,

		.init = hantro_jpeg_enc_init,

		.done = hantro_jpeg_enc_done,

		.exit = hantro_jpeg_enc_exit,

	},

	[HANTRO_MODE_H264_DEC] = {

		.run = hantro_g1_h264_dec_run,

		.reset = rk3066_vpu_dec_reset,

		.init = hantro_h264_dec_init,

		.exit = hantro_h264_dec_exit,

	},

	[HANTRO_MODE_MPEG2_DEC] = {

		.run = hantro_g1_mpeg2_dec_run,

		.reset = rk3066_vpu_dec_reset,

		.init = hantro_mpeg2_dec_init,

		.exit = hantro_mpeg2_dec_exit,

	},

	[HANTRO_MODE_VP8_DEC] = {

		.run = hantro_g1_vp8_dec_run,

		.reset = rk3066_vpu_dec_reset,

		.init = hantro_vp8_dec_init,

		.exit = hantro_vp8_dec_exit,

	},

};



static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {

	[HANTRO_MODE_JPEG_ENC] = {
@@ -301,10 +392,40 @@ static const struct hantro_irq rockchip_vpu2_irqs[] = { 
	{ "vdpu", rockchip_vpu2_vdpu_irq },

};



static const char * const rk3066_vpu_clk_names[] = {

	"aclk_vdpu", "hclk_vdpu",

	"aclk_vepu", "hclk_vepu"

};



static const char * const rockchip_vpu_clk_names[] = {

	"aclk", "hclk"

};



/*

 * Despite this variant has separate clocks for decoder and encoder,

 * it's still required to enable all four of them for either decoding

 * or encoding and we can't split it in separate g1/h1 variants.

 */

const struct hantro_variant rk3066_vpu_variant = {

	.enc_offset = 0x0,

	.enc_fmts = rockchip_vpu_enc_fmts,

	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),

	.dec_offset = 0x400,

	.dec_fmts = rk3066_vpu_dec_fmts,

	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),

	.postproc_fmts = rockchip_vpu1_postproc_fmts,

	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),

	.postproc_regs = &hantro_g1_postproc_regs,

	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |

		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,

	.codec_ops = rk3066_vpu_codec_ops,

	.irqs = rockchip_vpu1_irqs,

	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),

	.init = rk3066_vpu_hw_init,

	.clk_names = rk3066_vpu_clk_names,

	.num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)

};



const struct hantro_variant rk3288_vpu_variant = {

	.enc_offset = 0x0,

	.enc_fmts = rockchip_vpu_enc_fmts,