Commit c9caebd5 authored by Alex Bee's avatar Alex Bee Committed by Mauro Carvalho Chehab
Browse files

media: hantro: merge Rockchip platform drivers 

Merge the two Rockchip platform drivers into one as it was suggested at
[1] and [2].
This will hopefully make it easier to add new variants (which are surely
to come for Rockchip).
Also rename from "rk3288" to "v(d/e)pu1" and "rk3399" to "v(d/e)pu2"
where applicable, as this is the dicition the vendor uses and will
also refelect the variants that get added later in this series. Rename
from "rk3288" to "rockchip" if applicable to both hardware versions.

[1] https://patchwork.kernel.org/project/linux-rockchip/patch/20210107134101.195426-6-paul.kocialkowski@bootlin.com/
[2] https://patchwork.kernel.org/project/linux-rockchip/patch/20210525152225.154302-5-knaerzche@gmail.com/



Signed-off-by: default avatarAlex Bee <knaerzche@gmail.com>
Reviewed-by: default avatarEzequiel Garcia <ezequiel@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent 4b898fed

drivers/staging/media/hantro/Makefile

+4 −5
Original line number Diff line number Diff line
@@ -12,9 +12,9 @@ hantro-vpu-y += \ 
		hantro_g1_mpeg2_dec.o \

		hantro_g2_hevc_dec.o \

		hantro_g1_vp8_dec.o \

		rk3399_vpu_hw_jpeg_enc.o \

		rk3399_vpu_hw_mpeg2_dec.o \

		rk3399_vpu_hw_vp8_dec.o \

		rockchip_vpu2_hw_jpeg_enc.o \

		rockchip_vpu2_hw_mpeg2_dec.o \

		rockchip_vpu2_hw_vp8_dec.o \

		hantro_jpeg.o \

		hantro_h264.o \

		hantro_hevc.o \
@@ -28,5 +28,4 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \ 
		sama5d4_vdec_hw.o



hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \

		rk3288_vpu_hw.o \

		rk3399_vpu_hw.o
 
		rockchip_vpu_hw.o

drivers/staging/media/hantro/hantro_hw.h

+11 −11
Original line number Diff line number Diff line
@@ -191,16 +191,16 @@ struct hantro_codec_ops { 
/**

 * enum hantro_enc_fmt - source format ID for hardware registers.

 *

 * @RK3288_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format

 * @RK3288_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format

 * @RK3288_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV)

 * @RK3288_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY)

 * @ROCKCHIP_VPU_ENC_FMT_YUV420P: Y/CbCr 4:2:0 planar format

 * @ROCKCHIP_VPU_ENC_FMT_YUV420SP: Y/CbCr 4:2:0 semi-planar format

 * @ROCKCHIP_VPU_ENC_FMT_YUYV422: YUV 4:2:2 packed format (YUYV)

 * @ROCKCHIP_VPU_ENC_FMT_UYVY422: YUV 4:2:2 packed format (UYVY)

 */

enum hantro_enc_fmt {

	RK3288_VPU_ENC_FMT_YUV420P = 0,

	RK3288_VPU_ENC_FMT_YUV420SP = 1,

	RK3288_VPU_ENC_FMT_YUYV422 = 2,

	RK3288_VPU_ENC_FMT_UYVY422 = 3,

	ROCKCHIP_VPU_ENC_FMT_YUV420P = 0,

	ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1,

	ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2,

	ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,

};



extern const struct hantro_variant imx8mq_vpu_g2_variant;
@@ -225,7 +225,7 @@ irqreturn_t hantro_g1_irq(int irq, void *dev_id); 
void hantro_g1_reset(struct hantro_ctx *ctx);



int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);

int rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx);

int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx);

int hantro_jpeg_enc_init(struct hantro_ctx *ctx);

void hantro_jpeg_enc_exit(struct hantro_ctx *ctx);

void hantro_jpeg_enc_done(struct hantro_ctx *ctx);
@@ -274,14 +274,14 @@ hantro_h264_mv_size(unsigned int width, unsigned int height) 
}



int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);

int rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx);

int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);

void hantro_mpeg2_dec_copy_qtable(u8 *qtable,

				  const struct v4l2_ctrl_mpeg2_quantisation *ctrl);

int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);

void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);



int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx);

int rk3399_vpu_vp8_dec_run(struct hantro_ctx *ctx);

int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx);

int hantro_vp8_dec_init(struct hantro_ctx *ctx);

void hantro_vp8_dec_exit(struct hantro_ctx *ctx);

void hantro_vp8_prob_update(struct hantro_ctx *ctx,

drivers/staging/media/hantro/rk3399_vpu_hw.c

deleted100644 → 0
+0 −222
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Hantro VPU codec driver

 *

 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.

 *	Jeffy Chen <jeffy.chen@rock-chips.com>

 */



#include <linux/clk.h>



#include "hantro.h"

#include "hantro_jpeg.h"

#include "rk3399_vpu_regs.h"



#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)



/*

 * Supported formats.

 */



static const struct hantro_fmt rk3399_vpu_enc_fmts[] = {

	{

		.fourcc = V4L2_PIX_FMT_YUV420M,

		.codec_mode = HANTRO_MODE_NONE,

		.enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,

	},

	{

		.fourcc = V4L2_PIX_FMT_NV12M,

		.codec_mode = HANTRO_MODE_NONE,

		.enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,

	},

	{

		.fourcc = V4L2_PIX_FMT_YUYV,

		.codec_mode = HANTRO_MODE_NONE,

		.enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,

	},

	{

		.fourcc = V4L2_PIX_FMT_UYVY,

		.codec_mode = HANTRO_MODE_NONE,

		.enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,

	},

	{

		.fourcc = V4L2_PIX_FMT_JPEG,

		.codec_mode = HANTRO_MODE_JPEG_ENC,

		.max_depth = 2,

		.header_size = JPEG_HEADER_SIZE,

		.frmsize = {

			.min_width = 96,

			.max_width = 8192,

			.step_width = MB_DIM,

			.min_height = 32,

			.max_height = 8192,

			.step_height = MB_DIM,

		},

	},

};



static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {

	{

		.fourcc = V4L2_PIX_FMT_NV12,

		.codec_mode = HANTRO_MODE_NONE,

	},

	{

		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,

		.codec_mode = HANTRO_MODE_MPEG2_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 1920,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 1088,

			.step_height = MB_DIM,

		},

	},

	{

		.fourcc = V4L2_PIX_FMT_VP8_FRAME,

		.codec_mode = HANTRO_MODE_VP8_DEC,

		.max_depth = 2,

		.frmsize = {

			.min_width = 48,

			.max_width = 3840,

			.step_width = MB_DIM,

			.min_height = 48,

			.max_height = 2160,

			.step_height = MB_DIM,

		},

	},

};



static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)

{

	struct hantro_dev *vpu = dev_id;

	enum vb2_buffer_state state;

	u32 status;



	status = vepu_read(vpu, VEPU_REG_INTERRUPT);

	state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?

		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;



	vepu_write(vpu, 0, VEPU_REG_INTERRUPT);

	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);



	hantro_irq_done(vpu, state);



	return IRQ_HANDLED;

}



static irqreturn_t rk3399_vdpu_irq(int irq, void *dev_id)

{

	struct hantro_dev *vpu = dev_id;

	enum vb2_buffer_state state;

	u32 status;



	status = vdpu_read(vpu, VDPU_REG_INTERRUPT);

	state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?

		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;



	vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);

	vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);



	hantro_irq_done(vpu, state);



	return IRQ_HANDLED;

}



static int rk3399_vpu_hw_init(struct hantro_dev *vpu)

{

	/* Bump ACLK to max. possible freq. to improve performance. */

	clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);

	return 0;

}



static void rk3399_vpu_enc_reset(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;



	vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);

	vepu_write(vpu, 0, VEPU_REG_ENCODE_START);

	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);

}



static void rk3399_vpu_dec_reset(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;



	vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);

	vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);

	vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);

}



/*

 * Supported codec ops.

 */



static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {

	[HANTRO_MODE_JPEG_ENC] = {

		.run = rk3399_vpu_jpeg_enc_run,

		.reset = rk3399_vpu_enc_reset,

		.init = hantro_jpeg_enc_init,

		.exit = hantro_jpeg_enc_exit,

	},

	[HANTRO_MODE_MPEG2_DEC] = {

		.run = rk3399_vpu_mpeg2_dec_run,

		.reset = rk3399_vpu_dec_reset,

		.init = hantro_mpeg2_dec_init,

		.exit = hantro_mpeg2_dec_exit,

	},

	[HANTRO_MODE_VP8_DEC] = {

		.run = rk3399_vpu_vp8_dec_run,

		.reset = rk3399_vpu_dec_reset,

		.init = hantro_vp8_dec_init,

		.exit = hantro_vp8_dec_exit,

	},

};



/*

 * VPU variant.

 */



static const struct hantro_irq rk3399_irqs[] = {

	{ "vepu", rk3399_vepu_irq },

	{ "vdpu", rk3399_vdpu_irq },

};



static const char * const rk3399_clk_names[] = {

	"aclk", "hclk"

};



const struct hantro_variant rk3399_vpu_variant = {

	.enc_offset = 0x0,

	.enc_fmts = rk3399_vpu_enc_fmts,

	.num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),

	.dec_offset = 0x400,

	.dec_fmts = rk3399_vpu_dec_fmts,

	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),

	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |

		 HANTRO_VP8_DECODER,

	.codec_ops = rk3399_vpu_codec_ops,

	.irqs = rk3399_irqs,

	.num_irqs = ARRAY_SIZE(rk3399_irqs),

	.init = rk3399_vpu_hw_init,

	.clk_names = rk3399_clk_names,

	.num_clocks = ARRAY_SIZE(rk3399_clk_names)

};



static const struct hantro_irq rk3328_irqs[] = {

	{ "vdpu", rk3399_vdpu_irq },

};



const struct hantro_variant rk3328_vpu_variant = {

	.dec_offset = 0x400,

	.dec_fmts = rk3399_vpu_dec_fmts,

	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),

	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,

	.codec_ops = rk3399_vpu_codec_ops,

	.irqs = rk3328_irqs,

	.num_irqs = ARRAY_SIZE(rk3328_irqs),

	.init = rk3399_vpu_hw_init,

	.clk_names = rk3399_clk_names,

	.num_clocks = ARRAY_SIZE(rk3399_clk_names),

};

drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c→drivers/staging/media/hantro/rockchip_vpu2_hw_jpeg_enc.c

+15 −15
Original line number Diff line number Diff line
@@ -28,11 +28,11 @@ 
#include "hantro.h"

#include "hantro_v4l2.h"

#include "hantro_hw.h"

#include "rk3399_vpu_regs.h"

#include "rockchip_vpu2_regs.h"



#define VEPU_JPEG_QUANT_TABLE_COUNT 16



static void rk3399_vpu_set_src_img_ctrl(struct hantro_dev *vpu,

static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu,

					   struct hantro_ctx *ctx)

{

	struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
@@ -59,7 +59,7 @@ static void rk3399_vpu_set_src_img_ctrl(struct hantro_dev *vpu, 
	vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1);

}



static void rk3399_vpu_jpeg_enc_set_buffers(struct hantro_dev *vpu,

static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu,

					       struct hantro_ctx *ctx,

					       struct vb2_buffer *src_buf)

{
@@ -92,7 +92,7 @@ static void rk3399_vpu_jpeg_enc_set_buffers(struct hantro_dev *vpu, 
}



static void

rk3399_vpu_jpeg_enc_set_qtable(struct hantro_dev *vpu,

rockchip_vpu2_jpeg_enc_set_qtable(struct hantro_dev *vpu,

				  unsigned char *luma_qtable,

				  unsigned char *chroma_qtable)

{
@@ -118,7 +118,7 @@ rk3399_vpu_jpeg_enc_set_qtable(struct hantro_dev *vpu, 
	}

}



int rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx)

int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;

	struct vb2_v4l2_buffer *src_buf, *dst_buf;
@@ -141,9 +141,9 @@ int rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx) 
	vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG,

			   VEPU_REG_ENCODE_START);



	rk3399_vpu_set_src_img_ctrl(vpu, ctx);

	rk3399_vpu_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);

	rk3399_vpu_jpeg_enc_set_qtable(vpu,

	rockchip_vpu2_set_src_img_ctrl(vpu, ctx);

	rockchip_vpu2_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);

	rockchip_vpu2_jpeg_enc_set_qtable(vpu,

					  hantro_jpeg_get_qtable(0),

					  hantro_jpeg_get_qtable(1));

drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c→drivers/staging/media/hantro/rockchip_vpu2_hw_mpeg2_dec.c

+12 −13
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ 
#define VDPU_REG_MV_ACCURACY_BWD(v)	((v) ? BIT(1) : 0)



static void

rk3399_vpu_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,

rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu,

					 struct hantro_ctx *ctx)

{

	struct v4l2_ctrl_mpeg2_quantisation *q;
@@ -91,7 +91,7 @@ rk3399_vpu_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, 
}



static void

rk3399_vpu_mpeg2_dec_set_buffers(struct hantro_dev *vpu,

rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu,

				    struct hantro_ctx *ctx,

				    struct vb2_buffer *src_buf,

				    struct vb2_buffer *dst_buf,
@@ -148,7 +148,7 @@ rk3399_vpu_mpeg2_dec_set_buffers(struct hantro_dev *vpu, 
	vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);

}



int rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx)

int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx)

{

	struct hantro_dev *vpu = ctx->dev;

	struct vb2_v4l2_buffer *src_buf, *dst_buf;
@@ -233,11 +233,10 @@ int rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx) 
	      VDPU_REG_MV_ACCURACY_BWD(1);

	vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));



	rk3399_vpu_mpeg2_dec_set_quantisation(vpu, ctx);

	rockchip_vpu2_mpeg2_dec_set_quantisation(vpu, ctx);



	rk3399_vpu_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,

					 &dst_buf->vb2_buf,

					 seq, pic);

	rockchip_vpu2_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,

					    &dst_buf->vb2_buf, seq, pic);



	/* Kick the watchdog and start decoding */

	hantro_end_prepare_run(ctx);