Loading drivers/spi/spi-aspeed-smc.c +2 −2 Original line number Diff line number Diff line Loading @@ -1163,7 +1163,7 @@ static const struct aspeed_spi_data ast2500_spi_data = { static const struct aspeed_spi_data ast2600_fmc_data = { .max_cs = 3, .hastype = false, .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD, .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, .we0 = 16, .ctl0 = CE0_CTRL_REG, .timing = CE0_TIMING_COMPENSATION_REG, Loading @@ -1178,7 +1178,7 @@ static const struct aspeed_spi_data ast2600_fmc_data = { static const struct aspeed_spi_data ast2600_spi_data = { .max_cs = 2, .hastype = false, .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD, .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, .we0 = 16, .ctl0 = CE0_CTRL_REG, .timing = CE0_TIMING_COMPENSATION_REG, Loading drivers/spi/spi-gxp.c +1 −1 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0=or-later // SPDX-License-Identifier: GPL-2.0-or-later /* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */ #include <linux/iopoll.h> Loading drivers/spi/spi-intel.c +1 −1 Original line number Diff line number Diff line Loading @@ -114,7 +114,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) /* Flash descriptor fields */ #define FLVALSIG_MAGIC 0x0ff0a55a Loading drivers/spi/spi-mpc52xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -151,7 +151,7 @@ mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) int spr, sppr; u8 ctrl1; if (status && (irq != NO_IRQ)) if (status && irq) dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", status); Loading drivers/spi/spi-tegra210-quad.c +5 −0 Original line number Diff line number Diff line Loading @@ -1157,6 +1157,11 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, msg->actual_length += xfer->len; transfer_phase++; } if (!xfer->cs_change) { tegra_qspi_transfer_end(spi); spi_transfer_delay_exec(xfer); } ret = 0; exit: msg->status = ret; Loading Loading
drivers/spi/spi-aspeed-smc.c +2 −2 Original line number Diff line number Diff line Loading @@ -1163,7 +1163,7 @@ static const struct aspeed_spi_data ast2500_spi_data = { static const struct aspeed_spi_data ast2600_fmc_data = { .max_cs = 3, .hastype = false, .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD, .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, .we0 = 16, .ctl0 = CE0_CTRL_REG, .timing = CE0_TIMING_COMPENSATION_REG, Loading @@ -1178,7 +1178,7 @@ static const struct aspeed_spi_data ast2600_fmc_data = { static const struct aspeed_spi_data ast2600_spi_data = { .max_cs = 2, .hastype = false, .mode_bits = SPI_RX_QUAD | SPI_RX_QUAD, .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, .we0 = 16, .ctl0 = CE0_CTRL_REG, .timing = CE0_TIMING_COMPENSATION_REG, Loading
drivers/spi/spi-gxp.c +1 −1 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0=or-later // SPDX-License-Identifier: GPL-2.0-or-later /* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */ #include <linux/iopoll.h> Loading
drivers/spi/spi-intel.c +1 −1 Original line number Diff line number Diff line Loading @@ -114,7 +114,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) /* Flash descriptor fields */ #define FLVALSIG_MAGIC 0x0ff0a55a Loading
drivers/spi/spi-mpc52xx.c +1 −1 Original line number Diff line number Diff line Loading @@ -151,7 +151,7 @@ mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) int spr, sppr; u8 ctrl1; if (status && (irq != NO_IRQ)) if (status && irq) dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", status); Loading
drivers/spi/spi-tegra210-quad.c +5 −0 Original line number Diff line number Diff line Loading @@ -1157,6 +1157,11 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, msg->actual_length += xfer->len; transfer_phase++; } if (!xfer->cs_change) { tegra_qspi_transfer_end(spi); spi_transfer_delay_exec(xfer); } ret = 0; exit: msg->status = ret; Loading