Unverified Commit 6a43cd02 authored by Mauro Lima's avatar Mauro Lima Committed by Mark Brown
Browse files

spi: intel: Fix the offset to get the 64K erase opcode 



According to documentation, the 64K erase opcode is located in VSCC
range [16:23] instead of [8:15].
Use the proper value to shift the mask over the correct range.

Signed-off-by: default avatarMauro Lima <mauro.lima@eclypsium.com>
Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 5302e1ff

drivers/spi/spi-intel.c

+1 −1
Original line number Diff line number Diff line
@@ -114,7 +114,7 @@ 
#define ERASE_OPCODE_SHIFT		8

#define ERASE_OPCODE_MASK		(0xff << ERASE_OPCODE_SHIFT)

#define ERASE_64K_OPCODE_SHIFT		16

#define ERASE_64K_OPCODE_MASK		(0xff << ERASE_OPCODE_SHIFT)

#define ERASE_64K_OPCODE_MASK		(0xff << ERASE_64K_OPCODE_SHIFT)



/* Flash descriptor fields */

#define FLVALSIG_MAGIC			0x0ff0a55a