Unverified Commit 77caa0f8 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!3098 [OLK-6.6] Add support for Zhaoxin Processors 

Merge Pull Request from: @leoliu-oc 
 
Let Linux supports new Zhaoxin CPU features and "  Shanghai  " CPU vendor ID; 
let related drivers supports new Zhaoxin CPU FMS. 
Fix a CPU topo limitation of Installed kernel use CPUID B leaf to get CPU topo as default, 
add 4leaf get CPU cacheinfo additionally.

Note：
Support for the Zhaoxin processor includes two vendor IDs, zhaoxin and centaur, so we will synchronously modify centaur.c and zhaoxin.c.

Include:
1. x86/cpufeatures: Add Zhaoxin feature bits
2. x86/cpu: Add detect extended topology for Zhaoxin CPUs

## Test
1. Pass: cpu featrue flags is displayed correctly
2. Pass: Topology logic information is displayed correctly


### Issue
https://gitee.com/openeuler/kernel/issues/I8WS73

 
 
Link:https://gitee.com/openeuler/kernel/pulls/3098

 

Reviewed-by: default avatarAichun Shi <aichun.shi@intel.com>
Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents a662a03b 2028f308

arch/x86/include/asm/cpufeatures.h

+19 −0
Original line number Diff line number Diff line
@@ -148,6 +148,8 @@ 
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

#define X86_FEATURE_XSTORE		( 5*32+ 2) /* "rng" RNG present (xstore) */

#define X86_FEATURE_XSTORE_EN		( 5*32+ 3) /* "rng_en" RNG enabled */

#define X86_FEATURE_CCS        (5*32+4) /*  "sm3 sm4" present */

#define X86_FEATURE_CCS_EN		(5*32+5) /*  "sm3_en sm4_en" enabled */

#define X86_FEATURE_XCRYPT		( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */

#define X86_FEATURE_XCRYPT_EN		( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */

#define X86_FEATURE_ACE2		( 5*32+ 8) /* Advanced Cryptography Engine v2 */
@@ -156,6 +158,23 @@ 
#define X86_FEATURE_PHE_EN		( 5*32+11) /* PHE enabled */

#define X86_FEATURE_PMM			( 5*32+12) /* PadLock Montgomery Multiplier */

#define X86_FEATURE_PMM_EN		( 5*32+13) /* PMM enabled */

#define X86_FEATURE_ZX_FMA		(5*32+15) /* FMA supported */

#define X86_FEATURE_PARALLAX	(5*32+16) /* Adaptive P-state control present */

#define X86_FEATURE_PARALLAX_EN (5*32+17) /* Adaptive P-state control enabled */

#define X86_FEATURE_OVERSTRESS	(5*32+18) /* Overstress Feature for auto overclock present */

#define X86_FEATURE_OVERSTRESS_EN (5*32+19) /* Overstress Feature for auto overclock enabled */

#define X86_FEATURE_TM3        (5*32+20) /* Thermal Monitor 3 present */

#define X86_FEATURE_TM3_EN		(5*32+21) /* Thermal Monitor 3 enabled */

#define X86_FEATURE_RNG2		(5*32+22) /* 2nd generation of RNG present */

#define X86_FEATURE_RNG2_EN    (5*32+23) /* 2nd generation of RNG enabled */

#define X86_FEATURE_SEM        (5*32+24) /* SME feature present */

#define X86_FEATURE_PHE2		(5*32+25) /* SHA384 and SHA 512 present */

#define X86_FEATURE_PHE2_EN    (5*32+26) /* SHA384 and SHA 512 enabled */

#define X86_FEATURE_XMODX      (5*32+27) /* "rsa" XMODEXP and MONTMUL2 are present */

#define X86_FEATURE_XMODX_EN   (5*32+28) /* "rsa_en" XMODEXP and MONTMUL2 are enabled */

#define X86_FEATURE_VEX        (5*32+29) /* VEX instructions are present */

#define X86_FEATURE_VEX_EN		(5*32+30) /* VEX instructions are enabled */

#define X86_FEATURE_STK        (5*32+31) /* STK are present */



/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */

#define X86_FEATURE_LAHF_LM		( 6*32+ 0) /* LAHF/SAHF in long mode */

arch/x86/kernel/cpu/centaur.c

+7 −1
Original line number Diff line number Diff line
@@ -109,6 +109,9 @@ static void early_init_centaur(struct cpuinfo_x86 *c) 
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);

	}



	if (detect_extended_topology_early(c) < 0)

		detect_ht_early(c);

}



static void init_centaur(struct cpuinfo_x86 *c)
@@ -127,11 +130,14 @@ static void init_centaur(struct cpuinfo_x86 *c) 
	clear_cpu_cap(c, 0*32+31);

#endif

	early_init_centaur(c);

	detect_extended_topology(c);

	init_intel_cacheinfo(c);

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {

		detect_num_cpu_cores(c);

#ifdef CONFIG_X86_32

	detect_ht(c);

#endif

	}



	if (c->cpuid_level > 9) {

		unsigned int eax = cpuid_eax(10);

arch/x86/kernel/cpu/zhaoxin.c

+6 −1
Original line number Diff line number Diff line
@@ -79,16 +79,21 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c) 
			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);

	}



	if (detect_extended_topology_early(c) < 0)

		detect_ht_early(c);

}



static void init_zhaoxin(struct cpuinfo_x86 *c)

{

	early_init_zhaoxin(c);

	detect_extended_topology(c);

	init_intel_cacheinfo(c);

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {

		detect_num_cpu_cores(c);

#ifdef CONFIG_X86_32

	detect_ht(c);

#endif

	}



	if (c->cpuid_level > 9) {

		unsigned int eax = cpuid_eax(10);