Commit 76620567 authored by Shyam Sundar S K's avatar Shyam Sundar S K Committed by Hans de Goede
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platform/x86: amd-pmc: Add support for logging SMU metrics 



SMU provides a way to dump the s0ix debug statistics in the form of a
metrics table via a of set special mailbox commands.

Add support to the driver which can send these commands to SMU and expose
the information received via debugfs. The information contains the s0ix
entry/exit, active time of each IP block etc.

As a side note, SMU subsystem logging is not supported on Picasso based
SoC's.

Signed-off-by: default avatarShyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20210629084803.248498-5-Shyam-sundar.S-k@amd.com


Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent 162b937a

drivers/platform/x86/amd-pmc.c

+139 −8
Original line number Diff line number Diff line
@@ -46,6 +46,14 @@ 
#define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE

#define AMD_PMC_RESULT_FAILED                0xFF



/* SMU Message Definations */

#define SMU_MSG_GETSMUVERSION		0x02

#define SMU_MSG_LOG_GETDRAM_ADDR_HI	0x04

#define SMU_MSG_LOG_GETDRAM_ADDR_LO	0x05

#define SMU_MSG_LOG_START		0x06

#define SMU_MSG_LOG_RESET		0x07

#define SMU_MSG_LOG_DUMP_DATA		0x08

#define SMU_MSG_GET_SUP_CONSTRAINTS	0x09

/* List of supported CPU ids */

#define AMD_CPU_ID_RV			0x15D0

#define AMD_CPU_ID_RN			0x1630
@@ -55,17 +63,42 @@ 
#define PMC_MSG_DELAY_MIN_US		100

#define RESPONSE_REGISTER_LOOP_MAX	200



#define SOC_SUBSYSTEM_IP_MAX	12

#define DELAY_MIN_US		2000

#define DELAY_MAX_US		3000

enum amd_pmc_def {

	MSG_TEST = 0x01,

	MSG_OS_HINT_PCO,

	MSG_OS_HINT_RN,

};



struct amd_pmc_bit_map {

	const char *name;

	u32 bit_mask;

};



static const struct amd_pmc_bit_map soc15_ip_blk[] = {

	{"DISPLAY",	BIT(0)},

	{"CPU",		BIT(1)},

	{"GFX",		BIT(2)},

	{"VDD",		BIT(3)},

	{"ACP",		BIT(4)},

	{"VCN",		BIT(5)},

	{"ISP",		BIT(6)},

	{"NBIO",	BIT(7)},

	{"DF",		BIT(8)},

	{"USB0",	BIT(9)},

	{"USB1",	BIT(10)},

	{"LAPIC",	BIT(11)},

	{}

};



struct amd_pmc_dev {

	void __iomem *regbase;

	void __iomem *smu_base;

	void __iomem *smu_virt_addr;

	u32 base_addr;

	u32 cpu_id;

	u32 active_ips;

	struct device *dev;

	struct mutex lock; /* generic mutex lock */

#if IS_ENABLED(CONFIG_DEBUG_FS)
@@ -74,6 +107,7 @@ struct amd_pmc_dev { 
};



static struct amd_pmc_dev pmc;

static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret);



static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)

{
@@ -85,9 +119,49 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3 
	iowrite32(val, dev->regbase + reg_offset);

}



struct smu_metrics {

	u32 table_version;

	u32 hint_count;

	u32 s0i3_cyclecount;

	u32 timein_s0i2;

	u64 timeentering_s0i3_lastcapture;

	u64 timeentering_s0i3_totaltime;

	u64 timeto_resume_to_os_lastcapture;

	u64 timeto_resume_to_os_totaltime;

	u64 timein_s0i3_lastcapture;

	u64 timein_s0i3_totaltime;

	u64 timein_swdrips_lastcapture;

	u64 timein_swdrips_totaltime;

	u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];

	u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];

} __packed;



#ifdef CONFIG_DEBUG_FS

static int smu_fw_info_show(struct seq_file *s, void *unused)

{

	struct amd_pmc_dev *dev = s->private;

	struct smu_metrics table;

	int idx;



	if (dev->cpu_id == AMD_CPU_ID_PCO)

		return -EINVAL;



	memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));



	seq_puts(s, "\n=== SMU Statistics ===\n");

	seq_printf(s, "Table Version: %d\n", table.table_version);

	seq_printf(s, "Hint Count: %d\n", table.hint_count);

	seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount);

	seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);

	seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);



	seq_puts(s, "\n=== Active time (in us) ===\n");

	for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {

		if (soc15_ip_blk[idx].bit_mask & dev->active_ips)

			seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,

				   table.timecondition_notmet_lastcapture[idx]);

	}



	return 0;

}

DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
@@ -113,6 +187,32 @@ static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) 
}

#endif /* CONFIG_DEBUG_FS */



static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)

{

	u32 phys_addr_low, phys_addr_hi;

	u64 smu_phys_addr;



	if (dev->cpu_id == AMD_CPU_ID_PCO)

		return -EINVAL;



	/* Get Active devices list from SMU */

	amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);



	/* Get dram address */

	amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);

	amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);

	smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);



	dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));

	if (!dev->smu_virt_addr)

		return -ENOMEM;



	/* Start the logging */

	amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);



	return 0;

}



static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)

{

	u32 value;
@@ -127,10 +227,9 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) 
	dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);

}



static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set)

static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret)

{

	int rc;

	u8 msg;

	u32 val;



	mutex_lock(&dev->lock);
@@ -150,8 +249,8 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) 
	amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set);



	/* Write message ID to message ID register */

	msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO;

	amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);



	/* Wait until we get a valid response */

	rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,

				val, val != 0, PMC_MSG_DELAY_MIN_US,
@@ -163,6 +262,11 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) 


	switch (val) {

	case AMD_PMC_RESULT_OK:

		if (ret) {

			/* PMFW may take longer time to return back the data */

			usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);

			*data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);

		}

		break;

	case AMD_PMC_RESULT_CMD_REJECT_BUSY:

		dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
@@ -186,12 +290,29 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) 
	return rc;

}



static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)

{

	switch (dev->cpu_id) {

	case AMD_CPU_ID_PCO:

		return MSG_OS_HINT_PCO;

	case AMD_CPU_ID_RN:

		return MSG_OS_HINT_RN;

	}

	return -EINVAL;

}



static int __maybe_unused amd_pmc_suspend(struct device *dev)

{

	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);

	int rc;

	u8 msg;



	/* Reset and Start SMU logging - to monitor the s0i3 stats */

	amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);

	amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);



	rc = amd_pmc_send_cmd(pdev, 1);

	msg = amd_pmc_get_os_hint(pdev);

	rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0);

	if (rc)

		dev_err(pdev->dev, "suspend failed\n");
@@ -202,8 +323,13 @@ static int __maybe_unused amd_pmc_resume(struct device *dev) 
{

	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);

	int rc;

	u8 msg;



	/* Let SMU know that we are looking for stats */

	amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);



	rc = amd_pmc_send_cmd(pdev, 0);

	msg = amd_pmc_get_os_hint(pdev);

	rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);

	if (rc)

		dev_err(pdev->dev, "resume failed\n");
@@ -226,8 +352,7 @@ static int amd_pmc_probe(struct platform_device *pdev) 
{

	struct amd_pmc_dev *dev = &pmc;

	struct pci_dev *rdev;

	u32 base_addr_lo;

	u32 base_addr_hi;

	u32 base_addr_lo, base_addr_hi;

	u64 base_addr;

	int err;

	u32 val;
@@ -279,6 +404,12 @@ static int amd_pmc_probe(struct platform_device *pdev) 
		return -ENOMEM;



	mutex_init(&dev->lock);



	/* Use SMU to get the s0i3 debug stats */

	err = amd_pmc_setup_smu_logging(dev);

	if (err)

		dev_err(dev->dev, "SMU debugging info not supported on this platform\n");



	platform_set_drvdata(pdev, dev);

	amd_pmc_dbgfs_register(dev);

	return 0;