Unverified Commit 75ab93a2 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Zbb string optimizations" 

Heiko Stuebner <heiko@sntech.de> says:

From: Heiko Stuebner <heiko.stuebner@vrull.eu>

This series still tries to allow optimized string functions for specific
extensions. The last approach of using an inline base function to hold
the alternative calls did cause some issues in a number of places

So instead of that we're now just using an alternative j at the beginning
of the generic function to jump to a separate place inside the function
itself.

* b4-shazam-merge:
  RISC-V: add zbb support to string functions
  RISC-V: add infrastructure to allow different str* implementations

Link: https://lore.kernel.org/r/20230113212301.3534711-1-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 285b6a18 b6fcdb19

arch/riscv/Kconfig

+24 −0
Original line number Diff line number Diff line
@@ -416,6 +416,30 @@ config RISCV_ISA_SVPBMT 


	   If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZBB

	bool

	default y

	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb)

	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb)

	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900

	depends on AS_IS_GNU



config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

	depends on !XIP_KERNEL && MMU

	select RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the ZBB

	   extension (basic bit manipulation) and enable its usage.



	   The Zbb extension provides instructions to accelerate a number

	   of bit-specific operations (count bit population, sign extending,

	   bitrotation, etc).



	   If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZICBOM

	bool

	default y

arch/riscv/include/asm/errata_list.h

+2 −1
Original line number Diff line number Diff line
@@ -24,7 +24,8 @@ 


#define	CPUFEATURE_SVPBMT 0

#define	CPUFEATURE_ZICBOM 1

#define	CPUFEATURE_NUMBER 2

#define	CPUFEATURE_ZBB 2

#define	CPUFEATURE_NUMBER 3



#ifdef __ASSEMBLY__

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ enum riscv_isa_ext_id { 
	RISCV_ISA_EXT_SSTC,

	RISCV_ISA_EXT_SVINVAL,

	RISCV_ISA_EXT_SVPBMT,

	RISCV_ISA_EXT_ZBB,

	RISCV_ISA_EXT_ZICBOM,

	RISCV_ISA_EXT_ZIHINTPAUSE,

	RISCV_ISA_EXT_ID_MAX

arch/riscv/include/asm/string.h

+10 −0
Original line number Diff line number Diff line
@@ -18,6 +18,16 @@ extern asmlinkage void *__memcpy(void *, const void *, size_t); 
#define __HAVE_ARCH_MEMMOVE

extern asmlinkage void *memmove(void *, const void *, size_t);

extern asmlinkage void *__memmove(void *, const void *, size_t);



#define __HAVE_ARCH_STRCMP

extern asmlinkage int strcmp(const char *cs, const char *ct);



#define __HAVE_ARCH_STRLEN

extern asmlinkage __kernel_size_t strlen(const char *);



#define __HAVE_ARCH_STRNCMP

extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count);



/* For those files which don't want to check by kasan. */

#if defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__)

#define memcpy(dst, src, len) __memcpy(dst, src, len)

arch/riscv/kernel/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ arch_initcall(riscv_cpuinfo_init); 
 * New entries to this struct should follow the ordering rules described above.

 */

static struct riscv_isa_ext_data isa_ext_arr[] = {

	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),

	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),