Unverified Commit b6fcdb19 authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
Browse files

RISC-V: add zbb support to string functions 

Add handling for ZBB extension and add support for using it as a
variant for optimized string functions.

Support for the Zbb-str-variants is limited to the GNU-assembler
for now, as LLVM has not yet acquired the functionality to
selectively change the arch option in assembler code.
This is still under review at
    https://reviews.llvm.org/D123515



Co-developed-by: default avatarChristoph Muellner <christoph.muellner@vrull.eu>
Signed-off-by: default avatarChristoph Muellner <christoph.muellner@vrull.eu>
Signed-off-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230113212301.3534711-3-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 56e0790c

arch/riscv/Kconfig

+24 −0
Original line number Diff line number Diff line
@@ -416,6 +416,30 @@ config RISCV_ISA_SVPBMT 


	   If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZBB

	bool

	default y

	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb)

	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb)

	depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900

	depends on AS_IS_GNU



config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

	depends on !XIP_KERNEL && MMU

	select RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the ZBB

	   extension (basic bit manipulation) and enable its usage.



	   The Zbb extension provides instructions to accelerate a number

	   of bit-specific operations (count bit population, sign extending,

	   bitrotation, etc).



	   If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZICBOM

	bool

	default y

arch/riscv/include/asm/errata_list.h

+2 −1
Original line number Diff line number Diff line
@@ -24,7 +24,8 @@ 


#define	CPUFEATURE_SVPBMT 0

#define	CPUFEATURE_ZICBOM 1

#define	CPUFEATURE_NUMBER 2

#define	CPUFEATURE_ZBB 2

#define	CPUFEATURE_NUMBER 3



#ifdef __ASSEMBLY__

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ enum riscv_isa_ext_id { 
	RISCV_ISA_EXT_SSTC,

	RISCV_ISA_EXT_SVINVAL,

	RISCV_ISA_EXT_SVPBMT,

	RISCV_ISA_EXT_ZBB,

	RISCV_ISA_EXT_ZICBOM,

	RISCV_ISA_EXT_ZIHINTPAUSE,

	RISCV_ISA_EXT_ID_MAX

arch/riscv/kernel/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ arch_initcall(riscv_cpuinfo_init); 
 * New entries to this struct should follow the ordering rules described above.

 */

static struct riscv_isa_ext_data isa_ext_arr[] = {

	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),

	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),

arch/riscv/kernel/cpufeature.c

+18 −0
Original line number Diff line number Diff line
@@ -227,6 +227,7 @@ void __init riscv_fill_hwcap(void) 
				SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);

				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);

				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);

				SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);

				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);

				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);

			}
@@ -302,6 +303,20 @@ static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) 
	return true;

}



static bool __init_or_module cpufeature_probe_zbb(unsigned int stage)

{

	if (!IS_ENABLED(CONFIG_RISCV_ISA_ZBB))

		return false;



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return false;



	if (!riscv_isa_extension_available(NULL, ZBB))

		return false;



	return true;

}



/*

 * Probe presence of individual extensions.

 *
@@ -320,6 +335,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage) 
	if (cpufeature_probe_zicbom(stage))

		cpu_req_feature |= BIT(CPUFEATURE_ZICBOM);



	if (cpufeature_probe_zbb(stage))

		cpu_req_feature |= BIT(CPUFEATURE_ZBB);



	return cpu_req_feature;

}