Unverified Commit 756f4ae1 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynqmp-dt-for-v5.18' of https://github.com/Xilinx/linux-xlnx into arm/dt 

arm64: dts: ZynqMP DT changes for v5.18

- Dropping #stream-id-cells
- Add missing dma-cells and change dma node names

* tag 'zynqmp-dt-for-v5.18' of https://github.com/Xilinx/linux-xlnx:
  arm64: zynqmp: Rename dma to dma-controller
  arm64: zynqmp: Add missing #dma-cells property
  arm64: xilinx: dts: drop legacy property #stream-id-cells

Link: https://lore.kernel.org/r/19464dc6-eca9-f9a7-8aba-43af094d7c37@xilinx.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7d8e1702 3a14f0e6

arch/arm64/boot/dts/xilinx/zynqmp.dtsi

+32 −44
Original line number Diff line number Diff line
@@ -254,106 +254,106 @@ 
		};



		/* GDMA */

		fpd_dma_chan1: dma@fd500000 {

		fpd_dma_chan1: dma-controller@fd500000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd500000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 124 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14e8>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan2: dma@fd510000 {

		fpd_dma_chan2: dma-controller@fd510000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd510000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 125 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14e9>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan3: dma@fd520000 {

		fpd_dma_chan3: dma-controller@fd520000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd520000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 126 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14ea>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan4: dma@fd530000 {

		fpd_dma_chan4: dma-controller@fd530000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd530000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 127 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14eb>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan5: dma@fd540000 {

		fpd_dma_chan5: dma-controller@fd540000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd540000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 128 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14ec>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan6: dma@fd550000 {

		fpd_dma_chan6: dma-controller@fd550000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd550000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 129 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14ed>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan7: dma@fd560000 {

		fpd_dma_chan7: dma-controller@fd560000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd560000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 130 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14ee>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};



		fpd_dma_chan8: dma@fd570000 {

		fpd_dma_chan8: dma-controller@fd570000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xfd570000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 131 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <128>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x14ef>;

			power-domains = <&zynqmp_firmware PD_GDMA>;

		};
@@ -375,106 +375,106 @@ 
		 * These dma channels, Users should ensure that these dma

		 * Channels are allowed for non secure access.

		 */

		lpd_dma_chan1: dma@ffa80000 {

		lpd_dma_chan1: dma-controller@ffa80000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffa80000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 77 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x868>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan2: dma@ffa90000 {

		lpd_dma_chan2: dma-controller@ffa90000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffa90000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 78 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x869>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan3: dma@ffaa0000 {

		lpd_dma_chan3: dma-controller@ffaa0000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffaa0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 79 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x86a>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan4: dma@ffab0000 {

		lpd_dma_chan4: dma-controller@ffab0000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffab0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 80 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x86b>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan5: dma@ffac0000 {

		lpd_dma_chan5: dma-controller@ffac0000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffac0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 81 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x86c>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan6: dma@ffad0000 {

		lpd_dma_chan6: dma-controller@ffad0000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffad0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 82 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x86d>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan7: dma@ffae0000 {

		lpd_dma_chan7: dma-controller@ffae0000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffae0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 83 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x86e>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};



		lpd_dma_chan8: dma@ffaf0000 {

		lpd_dma_chan8: dma-controller@ffaf0000 {

			status = "disabled";

			compatible = "xlnx,zynqmp-dma-1.0";

			reg = <0x0 0xffaf0000 0x0 0x1000>;

			interrupt-parent = <&gic>;

			interrupts = <0 84 4>;

			clock-names = "clk_main", "clk_apb";

			#dma-cells = <1>;

			xlnx,bus-width = <64>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x86f>;

			power-domains = <&zynqmp_firmware PD_ADMA>;

		};
@@ -495,7 +495,6 @@ 
			interrupts = <0 14 4>;

			#address-cells = <1>;

			#size-cells = <0>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x872>;

			power-domains = <&zynqmp_firmware PD_NAND>;

		};
@@ -509,7 +508,6 @@ 
			clock-names = "pclk", "hclk", "tx_clk";

			#address-cells = <1>;

			#size-cells = <0>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x874>;

			power-domains = <&zynqmp_firmware PD_ETH_0>;

		};
@@ -523,7 +521,6 @@ 
			clock-names = "pclk", "hclk", "tx_clk";

			#address-cells = <1>;

			#size-cells = <0>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x875>;

			power-domains = <&zynqmp_firmware PD_ETH_1>;

		};
@@ -537,7 +534,6 @@ 
			clock-names = "pclk", "hclk", "tx_clk";

			#address-cells = <1>;

			#size-cells = <0>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x876>;

			power-domains = <&zynqmp_firmware PD_ETH_2>;

		};
@@ -551,7 +547,6 @@ 
			clock-names = "pclk", "hclk", "tx_clk";

			#address-cells = <1>;

			#size-cells = <0>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x877>;

			power-domains = <&zynqmp_firmware PD_ETH_3>;

		};
@@ -621,7 +616,6 @@ 
					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,

					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,

					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x4d0>;

			power-domains = <&zynqmp_firmware PD_PCIE>;

			pcie_intc: legacy-interrupt-controller {
@@ -642,7 +636,6 @@ 
			      <0x0 0xc0000000 0x0 0x8000000>;

			#address-cells = <1>;

			#size-cells = <0>;

			#stream-id-cells = <1>;

			iommus = <&smmu 0x873>;

			power-domains = <&zynqmp_firmware PD_QSPI>;

		};
@@ -674,7 +667,6 @@ 
			interrupts = <0 133 4>;

			power-domains = <&zynqmp_firmware PD_SATA>;

			resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;

			#stream-id-cells = <4>;

			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,

				 <&smmu 0x4c2>, <&smmu 0x4c3>;

		};
@@ -686,7 +678,6 @@ 
			interrupts = <0 48 4>;

			reg = <0x0 0xff160000 0x0 0x1000>;

			clock-names = "clk_xin", "clk_ahb";

			#stream-id-cells = <1>;

			iommus = <&smmu 0x870>;

			#clock-cells = <1>;

			clock-output-names = "clk_out_sd0", "clk_in_sd0";
@@ -700,7 +691,6 @@ 
			interrupts = <0 49 4>;

			reg = <0x0 0xff170000 0x0 0x1000>;

			clock-names = "clk_xin", "clk_ahb";

			#stream-id-cells = <1>;

			iommus = <&smmu 0x871>;

			#clock-cells = <1>;

			clock-output-names = "clk_out_sd1", "clk_in_sd1";
@@ -825,7 +815,6 @@ 
				interrupt-parent = <&gic>;

				interrupt-names = "dwc_usb3", "otg";

				interrupts = <0 65 4>, <0 69 4>;

				#stream-id-cells = <1>;

				iommus = <&smmu 0x860>;

				snps,quirk-frame-length-adjustment = <0x20>;

				/* dma-coherent; */
@@ -852,7 +841,6 @@ 
				interrupt-parent = <&gic>;

				interrupt-names = "dwc_usb3", "otg";

				interrupts = <0 70 4>, <0 74 4>;

				#stream-id-cells = <1>;

				iommus = <&smmu 0x861>;

				snps,quirk-frame-length-adjustment = <0x20>;

				/* dma-coherent; */