Unverified Commit 75665082 authored by Andre Przywara's avatar Andre Przywara Committed by Maxime Ripard
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clk: sunxi-ng: h6: Fix CEC clock 



The CEC clock on the H6 SoC is a bit special, since it uses a fixed
pre-dividier for one source clock (the PLL), but conveys the other clock
(32K OSC) directly.
We are using a fixed predivider array for that, but fail to use the right
flag to actually activate that.

Fixes: 524353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Reported-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210106143246.11255-1-andre.przywara@arm.com
parent 0482a4e6

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+1 −1
Original line number Diff line number Diff line
@@ -682,7 +682,7 @@ static struct ccu_mux hdmi_cec_clk = { 


	.common		= {

		.reg		= 0xb10,

		.features	= CCU_FEATURE_VARIABLE_PREDIV,

		.features	= CCU_FEATURE_FIXED_PREDIV,

		.hw.init	= CLK_HW_INIT_PARENTS("hdmi-cec",

						      hdmi_cec_parents,

						      &ccu_mux_ops,