Commit 0482a4e6 authored by Samuel Holland's avatar Samuel Holland Committed by Chen-Yu Tsai
Browse files

clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset 



While no information about the H6 RSB controller is included in the
datasheet or manual, the vendor BSP and power management blob both
reference the RSB clock parent and register address. These values were
verified by experimentation.

Since this clock/reset are added late, the specifier is added at the end
to maintain the existing DT binding. The code is kept in register order.

Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 5c8fe583

drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

+5 −0
Original line number Diff line number Diff line
@@ -91,6 +91,8 @@ static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2", 
		      0x18c, BIT(0), 0);

static SUNXI_CCU_GATE(r_apb2_i2c_clk,	"r-apb2-i2c",	"r-apb2",

		      0x19c, BIT(0), 0);

static SUNXI_CCU_GATE(r_apb2_rsb_clk,	"r-apb2-rsb",	"r-apb2",

		      0x1bc, BIT(0), 0);

static SUNXI_CCU_GATE(r_apb1_ir_clk,	"r-apb1-ir",	"r-apb1",

		      0x1cc, BIT(0), 0);

static SUNXI_CCU_GATE(r_apb1_w1_clk,	"r-apb1-w1",	"r-apb1",
@@ -130,6 +132,7 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = { 
	&r_apb1_pwm_clk.common,

	&r_apb2_uart_clk.common,

	&r_apb2_i2c_clk.common,

	&r_apb2_rsb_clk.common,

	&r_apb1_ir_clk.common,

	&r_apb1_w1_clk.common,

	&ir_clk.common,
@@ -147,6 +150,7 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { 
		[CLK_R_APB1_PWM]	= &r_apb1_pwm_clk.common.hw,

		[CLK_R_APB2_UART]	= &r_apb2_uart_clk.common.hw,

		[CLK_R_APB2_I2C]	= &r_apb2_i2c_clk.common.hw,

		[CLK_R_APB2_RSB]	= &r_apb2_rsb_clk.common.hw,

		[CLK_R_APB1_IR]		= &r_apb1_ir_clk.common.hw,

		[CLK_R_APB1_W1]		= &r_apb1_w1_clk.common.hw,

		[CLK_IR]		= &ir_clk.common.hw,
@@ -161,6 +165,7 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = { 
	[RST_R_APB1_PWM]	=  { 0x13c, BIT(16) },

	[RST_R_APB2_UART]	=  { 0x18c, BIT(16) },

	[RST_R_APB2_I2C]	=  { 0x19c, BIT(16) },

	[RST_R_APB2_RSB]	=  { 0x1bc, BIT(16) },

	[RST_R_APB1_IR]		=  { 0x1cc, BIT(16) },

	[RST_R_APB1_W1]		=  { 0x1ec, BIT(16) },

};

drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h

+1 −1
Original line number Diff line number Diff line
@@ -14,6 +14,6 @@ 


#define CLK_R_APB2	3



#define CLK_NUMBER	(CLK_W1 + 1)

#define CLK_NUMBER	(CLK_R_APB2_RSB + 1)



#endif /* _CCU_SUN50I_H6_R_H */

include/dt-bindings/clock/sun50i-h6-r-ccu.h

+2 −0
Original line number Diff line number Diff line
@@ -21,4 +21,6 @@ 
#define CLK_IR			11

#define CLK_W1			12



#define CLK_R_APB2_RSB		13



#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */

include/dt-bindings/reset/sun50i-h6-r-ccu.h

+1 −0
Original line number Diff line number Diff line
@@ -13,5 +13,6 @@ 
#define RST_R_APB2_I2C		4

#define RST_R_APB1_IR		5

#define RST_R_APB1_W1		6

#define RST_R_APB2_RSB		7



#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */