Commit 756344e7 authored Oct 18, 2022 by Yang Yingliang Committed by Conor Dooley Nov 09, 2022

soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

parent 73e770f0

drivers/soc/sifive/sifive_ccache.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void)
		NULL);
		if (rc) {
		pr_err("Could not request IRQ %d\n", g_irq[i]);
		goto err_unmap;
		goto err_free_irq;
		}
		}

		@@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void)
		#endif
		return 0;

		err_free_irq:
		while (--i >= 0)
		free_irq(g_irq[i], NULL);
		err_unmap:
		iounmap(ccache_base);
		return rc;