Commit 73e770f0 authored by Yang Yingliang's avatar Yang Yingliang Committed by Conor Dooley
Browse files

soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init() 



Add missing iounmap() before return error from sifive_ccache_init().

Fixes: a967a289 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 9abf2313

drivers/soc/sifive/sifive_ccache.c

+11 −4
Original line number Diff line number Diff line
@@ -222,13 +222,16 @@ static int __init sifive_ccache_init(void) 
	if (!ccache_base)

		return -ENOMEM;



	if (of_property_read_u32(np, "cache-level", &level))

		return -ENOENT;

	if (of_property_read_u32(np, "cache-level", &level)) {

		rc = -ENOENT;

		goto err_unmap;

	}



	intr_num = of_property_count_u32_elems(np, "interrupts");

	if (!intr_num) {

		pr_err("No interrupts property\n");

		return -ENODEV;

		rc = -ENODEV;

		goto err_unmap;

	}



	for (i = 0; i < intr_num; i++) {
@@ -237,7 +240,7 @@ static int __init sifive_ccache_init(void) 
				 NULL);

		if (rc) {

			pr_err("Could not request IRQ %d\n", g_irq[i]);

			return rc;

			goto err_unmap;

		}

	}
@@ -250,6 +253,10 @@ static int __init sifive_ccache_init(void) 
	setup_sifive_debug();

#endif

	return 0;



err_unmap:

	iounmap(ccache_base);

	return rc;

}



device_initcall(sifive_ccache_init);