Commit 74b66850 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvd0/disp: call into core to handle sor power state changes 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6c5a0424

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ struct nv50_disp_priv { 
	} dac;

	struct {

		int nr;

		int (*power)(struct nv50_disp_priv *, int sor, u32 data);

		int (*dp_train)(struct nv50_disp_priv *, int sor, int link,

				u16 type, u16 mask, u32 data,

				struct dcb_output *);
@@ -38,6 +39,7 @@ extern struct nouveau_omthds nva3_disp_base_omthds[]; 
#define SOR_MTHD(n) (n), (n) + 0x3f



int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);

int nv50_sor_power(struct nv50_disp_priv *, int, u32);



int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,

		      struct dcb_output *);

drivers/gpu/drm/nouveau/core/engine/disp/nva3.c

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ nva3_disp_sclass[] = { 


struct nouveau_omthds

nva3_disp_base_omthds[] = {

	{ SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_TRAIN)    , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_LNKCTL)   , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(0)), nv50_sor_mthd },

drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

+1 −0
Original line number Diff line number Diff line
@@ -896,6 +896,7 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	priv->head.nr = nv_rd32(priv, 0x022448);

	priv->dac.nr = 3;

	priv->sor.nr = 4;

	priv->sor.power = nv50_sor_power;

	priv->sor.dp_train = nvd0_sor_dp_train;

	priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;

	priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;

drivers/gpu/drm/nouveau/core/engine/disp/nve0.c

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	priv->head.nr = nv_rd32(priv, 0x022448);

	priv->dac.nr = 3;

	priv->sor.nr = 4;

	priv->sor.power = nv50_sor_power;

	priv->sor.dp_train = nvd0_sor_dp_train;

	priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;

	priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;

drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c

+16 −0
Original line number Diff line number Diff line
@@ -27,9 +27,22 @@ 


#include <subdev/bios.h>

#include <subdev/bios/dcb.h>

#include <subdev/timer.h>



#include "nv50.h"



int

nv50_sor_power(struct nv50_disp_priv *priv, int or, u32 data)

{

	const u32 stat = data & NV50_DISP_SOR_PWR_STATE;

	const u32 soff = (or * 0x800);

	nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);

	nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);

	nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);

	nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000);

	return 0;

}



int

nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)

{
@@ -72,6 +85,9 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) 


	data = *(u32 *)args;

	switch (mthd & ~0x3f) {

	case NV50_DISP_SOR_PWR:

		ret = priv->sor.power(priv, or, data);

		break;

	case NV94_DISP_SOR_DP_TRAIN:

		ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp);

		break;