Loading drivers/gpu/drm/nouveau/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -137,6 +137,8 @@ nouveau-y += core/engine/disp/nva0.o nouveau-y += core/engine/disp/nva3.o nouveau-y += core/engine/disp/nvd0.o nouveau-y += core/engine/disp/nve0.o nouveau-y += core/engine/disp/sornv50.o nouveau-y += core/engine/disp/sornvd0.o nouveau-y += core/engine/disp/vga.o nouveau-y += core/engine/fifo/base.o nouveau-y += core/engine/fifo/nv04.o Loading drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +24 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,8 @@ #include <engine/dmaobj.h> #include <engine/disp.h> struct dcb_output; struct nv50_disp_priv { struct nouveau_disp base; struct nouveau_oclass *sclass; Loading @@ -19,9 +21,31 @@ struct nv50_disp_priv { } dac; struct { int nr; int (*dp_train)(struct nv50_disp_priv *, int sor, int link, u16 type, u16 mask, u32 data, struct dcb_output *); int (*dp_lnkctl)(struct nv50_disp_priv *, int sor, int link, int head, u16 type, u16 mask, u32 data, struct dcb_output *); int (*dp_drvctl)(struct nv50_disp_priv *, int sor, int link, int lane, u16 type, u16 mask, u32 data, struct dcb_output *); } sor; }; extern struct nouveau_omthds nva3_disp_base_omthds[]; #define SOR_MTHD(n) (n), (n) + 0x3f int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32); int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32, struct dcb_output *); int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, struct dcb_output *); int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, struct dcb_output *); struct nv50_disp_base { struct nouveau_parent base; struct nouveau_ramht *ramht; Loading drivers/gpu/drm/nouveau/core/engine/disp/nva3.c +11 −0 Original line number Diff line number Diff line Loading @@ -39,6 +39,17 @@ nva3_disp_sclass[] = { {} }; struct nouveau_omthds nva3_disp_base_omthds[] = { { SOR_MTHD(NV94_DISP_SOR_DP_TRAIN) , nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_LNKCTL) , nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(0)), nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(1)), nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(2)), nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(3)), nv50_sor_mthd }, {}, }; static struct nouveau_oclass nva3_disp_base_oclass[] = { { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs }, Loading drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +4 −1 Original line number Diff line number Diff line Loading @@ -552,7 +552,7 @@ nvd0_disp_base_ofuncs = { static struct nouveau_oclass nvd0_disp_base_oclass[] = { { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs }, { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, {} }; Loading Loading @@ -896,6 +896,9 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = nv_rd32(priv, 0x022448); priv->dac.nr = 3; priv->sor.nr = 4; priv->sor.dp_train = nvd0_sor_dp_train; priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl; priv->sor.dp_drvctl = nvd0_sor_dp_drvctl; INIT_LIST_HEAD(&priv->base.vblank.list); spin_lock_init(&priv->base.vblank.lock); Loading drivers/gpu/drm/nouveau/core/engine/disp/nve0.c +4 −1 Original line number Diff line number Diff line Loading @@ -41,7 +41,7 @@ nve0_disp_sclass[] = { static struct nouveau_oclass nve0_disp_base_oclass[] = { { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs }, { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, {} }; Loading @@ -66,6 +66,9 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = nv_rd32(priv, 0x022448); priv->dac.nr = 3; priv->sor.nr = 4; priv->sor.dp_train = nvd0_sor_dp_train; priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl; priv->sor.dp_drvctl = nvd0_sor_dp_drvctl; INIT_LIST_HEAD(&priv->base.vblank.list); spin_lock_init(&priv->base.vblank.lock); Loading Loading
drivers/gpu/drm/nouveau/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -137,6 +137,8 @@ nouveau-y += core/engine/disp/nva0.o nouveau-y += core/engine/disp/nva3.o nouveau-y += core/engine/disp/nvd0.o nouveau-y += core/engine/disp/nve0.o nouveau-y += core/engine/disp/sornv50.o nouveau-y += core/engine/disp/sornvd0.o nouveau-y += core/engine/disp/vga.o nouveau-y += core/engine/fifo/base.o nouveau-y += core/engine/fifo/nv04.o Loading
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +24 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,8 @@ #include <engine/dmaobj.h> #include <engine/disp.h> struct dcb_output; struct nv50_disp_priv { struct nouveau_disp base; struct nouveau_oclass *sclass; Loading @@ -19,9 +21,31 @@ struct nv50_disp_priv { } dac; struct { int nr; int (*dp_train)(struct nv50_disp_priv *, int sor, int link, u16 type, u16 mask, u32 data, struct dcb_output *); int (*dp_lnkctl)(struct nv50_disp_priv *, int sor, int link, int head, u16 type, u16 mask, u32 data, struct dcb_output *); int (*dp_drvctl)(struct nv50_disp_priv *, int sor, int link, int lane, u16 type, u16 mask, u32 data, struct dcb_output *); } sor; }; extern struct nouveau_omthds nva3_disp_base_omthds[]; #define SOR_MTHD(n) (n), (n) + 0x3f int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32); int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32, struct dcb_output *); int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, struct dcb_output *); int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, struct dcb_output *); struct nv50_disp_base { struct nouveau_parent base; struct nouveau_ramht *ramht; Loading
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c +11 −0 Original line number Diff line number Diff line Loading @@ -39,6 +39,17 @@ nva3_disp_sclass[] = { {} }; struct nouveau_omthds nva3_disp_base_omthds[] = { { SOR_MTHD(NV94_DISP_SOR_DP_TRAIN) , nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_LNKCTL) , nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(0)), nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(1)), nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(2)), nv50_sor_mthd }, { SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(3)), nv50_sor_mthd }, {}, }; static struct nouveau_oclass nva3_disp_base_oclass[] = { { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs }, Loading
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +4 −1 Original line number Diff line number Diff line Loading @@ -552,7 +552,7 @@ nvd0_disp_base_ofuncs = { static struct nouveau_oclass nvd0_disp_base_oclass[] = { { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs }, { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, {} }; Loading Loading @@ -896,6 +896,9 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = nv_rd32(priv, 0x022448); priv->dac.nr = 3; priv->sor.nr = 4; priv->sor.dp_train = nvd0_sor_dp_train; priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl; priv->sor.dp_drvctl = nvd0_sor_dp_drvctl; INIT_LIST_HEAD(&priv->base.vblank.list); spin_lock_init(&priv->base.vblank.lock); Loading
drivers/gpu/drm/nouveau/core/engine/disp/nve0.c +4 −1 Original line number Diff line number Diff line Loading @@ -41,7 +41,7 @@ nve0_disp_sclass[] = { static struct nouveau_oclass nve0_disp_base_oclass[] = { { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs }, { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds }, {} }; Loading @@ -66,6 +66,9 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->head.nr = nv_rd32(priv, 0x022448); priv->dac.nr = 3; priv->sor.nr = 4; priv->sor.dp_train = nvd0_sor_dp_train; priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl; priv->sor.dp_drvctl = nvd0_sor_dp_drvctl; INIT_LIST_HEAD(&priv->base.vblank.list); spin_lock_init(&priv->base.vblank.lock); Loading