Loading drivers/gpu/drm/nouveau/core/engine/graph/nv04.c +92 −92 Original line number Original line Diff line number Diff line Loading @@ -787,168 +787,168 @@ nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv03_graph_gdi_omthds[] = { nv03_graph_gdi_omthds[] = { { 0x0184, nv01_graph_mthd_bind_patt }, { 0x0184, 0x0184, nv01_graph_mthd_bind_patt }, { 0x0188, nv04_graph_mthd_bind_rop }, { 0x0188, 0x0188, nv04_graph_mthd_bind_rop }, { 0x018c, nv04_graph_mthd_bind_beta1 }, { 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 }, { 0x0190, nv04_graph_mthd_bind_surf_dst }, { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_gdi_omthds[] = { nv04_graph_gdi_omthds[] = { { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv01_graph_blit_omthds[] = { nv01_graph_blit_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv01_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x019c, nv04_graph_mthd_bind_surf_src }, { 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_blit_omthds[] = { nv04_graph_blit_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv04_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_iifc_omthds[] = { nv04_graph_iifc_omthds[] = { { 0x0188, nv01_graph_mthd_bind_chroma }, { 0x0188, 0x0188, nv01_graph_mthd_bind_chroma }, { 0x018c, nv01_graph_mthd_bind_clip }, { 0x018c, 0x018c, nv01_graph_mthd_bind_clip }, { 0x0190, nv04_graph_mthd_bind_patt }, { 0x0190, 0x0190, nv04_graph_mthd_bind_patt }, { 0x0194, nv04_graph_mthd_bind_rop }, { 0x0194, 0x0194, nv04_graph_mthd_bind_rop }, { 0x0198, nv04_graph_mthd_bind_beta1 }, { 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 }, { 0x019c, nv04_graph_mthd_bind_beta4 }, { 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 }, { 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, { 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, { 0x03e4, nv04_graph_mthd_set_operation }, { 0x03e4, 0x03e4, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv01_graph_ifc_omthds[] = { nv01_graph_ifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv01_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_ifc_omthds[] = { nv04_graph_ifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv04_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv03_graph_sifc_omthds[] = { nv03_graph_sifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_sifc_omthds[] = { nv04_graph_sifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv03_graph_sifm_omthds[] = { nv03_graph_sifm_omthds[] = { { 0x0188, nv01_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0304, nv04_graph_mthd_set_operation }, { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_sifm_omthds[] = { nv04_graph_sifm_omthds[] = { { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0304, nv04_graph_mthd_set_operation }, { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_surf3d_omthds[] = { nv04_graph_surf3d_omthds[] = { { 0x02f8, nv04_graph_mthd_surf3d_clip_h }, { 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h }, { 0x02fc, nv04_graph_mthd_surf3d_clip_v }, { 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv03_graph_ttri_omthds[] = { nv03_graph_ttri_omthds[] = { { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv04_graph_mthd_bind_surf_color }, { 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color }, { 0x0190, nv04_graph_mthd_bind_surf_zeta }, { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv01_graph_prim_omthds[] = { nv01_graph_prim_omthds[] = { { 0x0184, nv01_graph_mthd_bind_clip }, { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, { 0x0188, nv01_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_prim_omthds[] = { nv04_graph_prim_omthds[] = { { 0x0184, nv01_graph_mthd_bind_clip }, { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; Loading drivers/gpu/drm/nouveau/core/engine/graph/nv10.c +5 −5 Original line number Original line Diff line number Diff line Loading @@ -570,11 +570,11 @@ nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv17_celcius_omthds[] = { nv17_celcius_omthds[] = { { 0x1638, nv17_graph_mthd_lma_window }, { 0x1638, 0x1638, nv17_graph_mthd_lma_window }, { 0x163c, nv17_graph_mthd_lma_window }, { 0x163c, 0x163c, nv17_graph_mthd_lma_window }, { 0x1640, nv17_graph_mthd_lma_window }, { 0x1640, 0x1640, nv17_graph_mthd_lma_window }, { 0x1644, nv17_graph_mthd_lma_window }, { 0x1644, 0x1644, nv17_graph_mthd_lma_window }, { 0x1658, nv17_graph_mthd_lma_enable }, { 0x1658, 0x1658, nv17_graph_mthd_lma_enable }, {} {} }; }; Loading drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +3 −3 Original line number Original line Diff line number Diff line Loading @@ -121,9 +121,9 @@ nv31_mpeg_ofuncs = { static struct nouveau_omthds static struct nouveau_omthds nv31_mpeg_omthds[] = { nv31_mpeg_omthds[] = { { 0x0190, nv31_mpeg_mthd_dma }, { 0x0190, 0x0190, nv31_mpeg_mthd_dma }, { 0x01a0, nv31_mpeg_mthd_dma }, { 0x01a0, 0x01a0, nv31_mpeg_mthd_dma }, { 0x01b0, nv31_mpeg_mthd_dma }, { 0x01b0, 0x01b0, nv31_mpeg_mthd_dma }, {} {} }; }; Loading drivers/gpu/drm/nouveau/core/engine/software/nv04.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -63,8 +63,8 @@ nv04_software_flip(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv04_software_omthds[] = { nv04_software_omthds[] = { { 0x0150, nv04_software_set_ref }, { 0x0150, 0x0150, nv04_software_set_ref }, { 0x0500, nv04_software_flip }, { 0x0500, 0x0500, nv04_software_flip }, {} {} }; }; Loading drivers/gpu/drm/nouveau/core/engine/software/nv10.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -52,7 +52,7 @@ nv10_software_flip(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv10_software_omthds[] = { nv10_software_omthds[] = { { 0x0500, nv10_software_flip }, { 0x0500, 0x0500, nv10_software_flip }, {} {} }; }; Loading Loading
drivers/gpu/drm/nouveau/core/engine/graph/nv04.c +92 −92 Original line number Original line Diff line number Diff line Loading @@ -787,168 +787,168 @@ nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv03_graph_gdi_omthds[] = { nv03_graph_gdi_omthds[] = { { 0x0184, nv01_graph_mthd_bind_patt }, { 0x0184, 0x0184, nv01_graph_mthd_bind_patt }, { 0x0188, nv04_graph_mthd_bind_rop }, { 0x0188, 0x0188, nv04_graph_mthd_bind_rop }, { 0x018c, nv04_graph_mthd_bind_beta1 }, { 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 }, { 0x0190, nv04_graph_mthd_bind_surf_dst }, { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_gdi_omthds[] = { nv04_graph_gdi_omthds[] = { { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv01_graph_blit_omthds[] = { nv01_graph_blit_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv01_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x019c, nv04_graph_mthd_bind_surf_src }, { 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_blit_omthds[] = { nv04_graph_blit_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv04_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_iifc_omthds[] = { nv04_graph_iifc_omthds[] = { { 0x0188, nv01_graph_mthd_bind_chroma }, { 0x0188, 0x0188, nv01_graph_mthd_bind_chroma }, { 0x018c, nv01_graph_mthd_bind_clip }, { 0x018c, 0x018c, nv01_graph_mthd_bind_clip }, { 0x0190, nv04_graph_mthd_bind_patt }, { 0x0190, 0x0190, nv04_graph_mthd_bind_patt }, { 0x0194, nv04_graph_mthd_bind_rop }, { 0x0194, 0x0194, nv04_graph_mthd_bind_rop }, { 0x0198, nv04_graph_mthd_bind_beta1 }, { 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 }, { 0x019c, nv04_graph_mthd_bind_beta4 }, { 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 }, { 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, { 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, { 0x03e4, nv04_graph_mthd_set_operation }, { 0x03e4, 0x03e4, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv01_graph_ifc_omthds[] = { nv01_graph_ifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv01_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_ifc_omthds[] = { nv04_graph_ifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv04_graph_mthd_bind_patt }, { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, { 0x0190, nv04_graph_mthd_bind_rop }, { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, { 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, { 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, { 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv03_graph_sifc_omthds[] = { nv03_graph_sifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv01_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_sifc_omthds[] = { nv04_graph_sifc_omthds[] = { { 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv03_graph_sifm_omthds[] = { nv03_graph_sifm_omthds[] = { { 0x0188, nv01_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0304, nv04_graph_mthd_set_operation }, { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_sifm_omthds[] = { nv04_graph_sifm_omthds[] = { { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0304, nv04_graph_mthd_set_operation }, { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_surf3d_omthds[] = { nv04_graph_surf3d_omthds[] = { { 0x02f8, nv04_graph_mthd_surf3d_clip_h }, { 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h }, { 0x02fc, nv04_graph_mthd_surf3d_clip_v }, { 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv03_graph_ttri_omthds[] = { nv03_graph_ttri_omthds[] = { { 0x0188, nv01_graph_mthd_bind_clip }, { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, { 0x018c, nv04_graph_mthd_bind_surf_color }, { 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color }, { 0x0190, nv04_graph_mthd_bind_surf_zeta }, { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv01_graph_prim_omthds[] = { nv01_graph_prim_omthds[] = { { 0x0184, nv01_graph_mthd_bind_clip }, { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, { 0x0188, nv01_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; static struct nouveau_omthds static struct nouveau_omthds nv04_graph_prim_omthds[] = { nv04_graph_prim_omthds[] = { { 0x0184, nv01_graph_mthd_bind_clip }, { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, { 0x0188, nv04_graph_mthd_bind_patt }, { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, { 0x018c, nv04_graph_mthd_bind_rop }, { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, { 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, { 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, { 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, { 0x02fc, nv04_graph_mthd_set_operation }, { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, {} {} }; }; Loading
drivers/gpu/drm/nouveau/core/engine/graph/nv10.c +5 −5 Original line number Original line Diff line number Diff line Loading @@ -570,11 +570,11 @@ nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv17_celcius_omthds[] = { nv17_celcius_omthds[] = { { 0x1638, nv17_graph_mthd_lma_window }, { 0x1638, 0x1638, nv17_graph_mthd_lma_window }, { 0x163c, nv17_graph_mthd_lma_window }, { 0x163c, 0x163c, nv17_graph_mthd_lma_window }, { 0x1640, nv17_graph_mthd_lma_window }, { 0x1640, 0x1640, nv17_graph_mthd_lma_window }, { 0x1644, nv17_graph_mthd_lma_window }, { 0x1644, 0x1644, nv17_graph_mthd_lma_window }, { 0x1658, nv17_graph_mthd_lma_enable }, { 0x1658, 0x1658, nv17_graph_mthd_lma_enable }, {} {} }; }; Loading
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +3 −3 Original line number Original line Diff line number Diff line Loading @@ -121,9 +121,9 @@ nv31_mpeg_ofuncs = { static struct nouveau_omthds static struct nouveau_omthds nv31_mpeg_omthds[] = { nv31_mpeg_omthds[] = { { 0x0190, nv31_mpeg_mthd_dma }, { 0x0190, 0x0190, nv31_mpeg_mthd_dma }, { 0x01a0, nv31_mpeg_mthd_dma }, { 0x01a0, 0x01a0, nv31_mpeg_mthd_dma }, { 0x01b0, nv31_mpeg_mthd_dma }, { 0x01b0, 0x01b0, nv31_mpeg_mthd_dma }, {} {} }; }; Loading
drivers/gpu/drm/nouveau/core/engine/software/nv04.c +2 −2 Original line number Original line Diff line number Diff line Loading @@ -63,8 +63,8 @@ nv04_software_flip(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv04_software_omthds[] = { nv04_software_omthds[] = { { 0x0150, nv04_software_set_ref }, { 0x0150, 0x0150, nv04_software_set_ref }, { 0x0500, nv04_software_flip }, { 0x0500, 0x0500, nv04_software_flip }, {} {} }; }; Loading
drivers/gpu/drm/nouveau/core/engine/software/nv10.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -52,7 +52,7 @@ nv10_software_flip(struct nouveau_object *object, u32 mthd, static struct nouveau_omthds static struct nouveau_omthds nv10_software_omthds[] = { nv10_software_omthds[] = { { 0x0500, nv10_software_flip }, { 0x0500, 0x0500, nv10_software_flip }, {} {} }; }; Loading