Commit 74458c08 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN3.1 DML calculation support 



DML (Display mode library) is used for calculating watermarks, bandwidth
and for validating display configurations.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ba5a5371

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+39 −0
Original line number Diff line number Diff line
@@ -3070,6 +3070,18 @@ static void dcn20_calculate_wm( 
	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;

}



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)

{

	int i;

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

	}

	return false;

}

#endif



void dcn20_calculate_dlg_params(

		struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes,
@@ -3077,6 +3089,9 @@ void dcn20_calculate_dlg_params( 
		int vlevel)

{

	int i, pipe_idx;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	int plane_count;

#endif



	/* Writeback MCIF_WB arbitration parameters */

	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -3091,6 +3106,21 @@ void dcn20_calculate_dlg_params( 
		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]

							!= dm_dram_clock_change_unsupported;

	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ?

			DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW;



	plane_count = 0;

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (context->res_ctx.pipe_ctx[i].plane_state)

			plane_count++;

	}



	if (plane_count == 0)

		context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;



	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);

#endif



	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
@@ -3102,6 +3132,10 @@ void dcn20_calculate_dlg_params( 
		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;

			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;

#endif

		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
@@ -3115,6 +3149,11 @@ void dcn20_calculate_dlg_params( 
	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;

	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes

						- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;

#endif



	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;

drivers/gpu/drm/amd/display/dc/dml/Makefile

+11 −0
Original line number Diff line number Diff line
@@ -62,6 +62,10 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) 
CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048

CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)

ifdef CONFIG_DRM_AMD_DC_DCN3_1

CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) -Wframe-larger-than=2048

CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)

endif

CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
@@ -72,6 +76,10 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags) 
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)

ifdef CONFIG_DRM_AMD_DC_DCN3_1

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)

endif

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)

endif

CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
@@ -86,6 +94,9 @@ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_ 
DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o

DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o

DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o

ifdef CONFIG_DRM_AMD_DC_DCN3_1

DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o

endif

endif



AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

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+7506 −0

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drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h

0 → 100644
+43 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2017 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DML31_DISPLAY_MODE_VBA_H__

#define __DML31_DISPLAY_MODE_VBA_H__



void dml31_recalculate(struct display_mode_lib *mode_lib);

void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);

double dml31_CalculateWriteBackDISPCLK(

		enum source_format_class WritebackPixelFormat,

		double PixelClock,

		double WritebackHRatio,

		double WritebackVRatio,

		unsigned int WritebackHTaps,

		unsigned int WritebackVTaps,

		long   WritebackSourceWidth,

		long   WritebackDestinationWidth,

		unsigned int HTotal,

		unsigned int WritebackLineBufferSize);



#endif /* __DML31_DISPLAY_MODE_VBA_H__ */

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

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+1727 −0

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