Commit ba5a5371 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN3.1 DCHHUB 



Adds DCN3.1 DCHHUB programming and modifies DCN20/DCN30 shared
hardware sequencer helpers to use these hooks.

HW Blocks:

 +--------++------+       +----------+
 |DCHUBBUB|| HUBP |  <--  | MMHUBBUB |
 +--------++------+       +----------+
        |                      ^
        v                      |
    +--------+             +--------+
    |  DPP   | <---------> |  DWB   |
    +--------+             +--------+
        |                      ^
        v                      |
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+                  |
    |  OPP  |                  |
    +-------+                  |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

No changes to MMHUBBUB or DWB programming, added to diagram for clarity.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 110d3968

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+48 −0
Original line number Diff line number Diff line
@@ -139,6 +139,23 @@ struct dcn_hubbub_registers { 
	uint32_t DCHVM_CLK_CTRL;

	uint32_t DCHVM_RIOMMU_CTRL0;

	uint32_t DCHVM_RIOMMU_STAT0;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	uint32_t DCHUBBUB_DET0_CTRL;

	uint32_t DCHUBBUB_DET1_CTRL;

	uint32_t DCHUBBUB_DET2_CTRL;

	uint32_t DCHUBBUB_DET3_CTRL;

	uint32_t DCHUBBUB_COMPBUF_CTRL;

	uint32_t COMPBUF_RESERVED_SPACE;

	uint32_t DCHUBBUB_DEBUG_CTRL_0;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;

#endif

};



/* set field name */
@@ -275,17 +292,48 @@ struct dcn_hubbub_registers { 
		type HOSTVM_POWERSTATUS; \

		type RIOMMU_ACTIVE; \

		type HOSTVM_PREFETCH_DONE

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

#define HUBBUB_RET_REG_FIELD_LIST(type) \

		type DET_DEPTH;\

		type DET0_SIZE;\

		type DET1_SIZE;\

		type DET2_SIZE;\

		type DET3_SIZE;\

		type DET0_SIZE_CURRENT;\

		type DET1_SIZE_CURRENT;\

		type DET2_SIZE_CURRENT;\

		type DET3_SIZE_CURRENT;\

		type COMPBUF_SIZE;\

		type COMPBUF_SIZE_CURRENT;\

		type COMPBUF_RESERVED_SPACE_64B;\

		type COMPBUF_RESERVED_SPACE_ZS;\

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D

#endif





struct dcn_hubbub_shift {

	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);

	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);

	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	HUBBUB_RET_REG_FIELD_LIST(uint8_t);

#endif

};



struct dcn_hubbub_mask {

	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);

	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);

	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	HUBBUB_RET_REG_FIELD_LIST(uint32_t);

#endif

};



struct dc;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h

+9 −0
Original line number Diff line number Diff line
@@ -83,6 +83,15 @@ struct dcn20_hubbub { 
	int num_vmid;

	struct dcn20_vmid vmid[16];

	unsigned int detile_buf_size;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	unsigned int crb_size_segs;

	unsigned int compbuf_size_segments;

	unsigned int pixel_chunk_size;

	unsigned int det0_size;

	unsigned int det1_size;

	unsigned int det2_size;

	unsigned int det3_size;

#endif

};



void hubbub2_construct(struct dcn20_hubbub *hubbub,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h

+16 −0
Original line number Diff line number Diff line
@@ -216,16 +216,32 @@ 
	type ROW_TTU_MODE; \

	type NUM_PKRS



#ifdef CONFIG_DRM_AMD_DC_DCN3_1

#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \

	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\

	type HUBP_UNBOUNDED_REQ_MODE;\

	type CURSOR_REQ_MODE;\

	type HUBP_SOFT_RESET

#endif



struct dcn_hubp2_registers {

	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;

};



struct dcn_hubp2_shift {

#if   defined(CONFIG_DRM_AMD_DC_DCN3_1)

	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);

#else

	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);

#endif

};



struct dcn_hubp2_mask {

#if   defined(CONFIG_DRM_AMD_DC_DCN3_1)

	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);

#else

	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);

#endif

};



struct dcn20_hubp {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+37 −0
Original line number Diff line number Diff line
@@ -1269,6 +1269,9 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx 
		new_pipe->update_flags.bits.gamut_remap = 1;

		new_pipe->update_flags.bits.scaler = 1;

		new_pipe->update_flags.bits.viewport = 1;

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

		new_pipe->update_flags.bits.det_size = 1;

#endif

		if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {

			new_pipe->update_flags.bits.odm = 1;

			new_pipe->update_flags.bits.global_sync = 1;
@@ -1303,6 +1306,10 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx 
			new_pipe->update_flags.bits.global_sync = 1;

	}



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)

		new_pipe->update_flags.bits.det_size = 1;

#endif

	/*

	 * Detect opp / tg change, only set on change, not on enable

	 * Assume mpcc inst = pipe index, if not this code needs to be updated
@@ -1418,6 +1425,10 @@ static void dcn20_update_dchubp_dpp( 
			&pipe_ctx->ttu_regs,

			&pipe_ctx->rq_regs,

			&pipe_ctx->pipe_dlg_param);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

		if (hubp->funcs->set_unbounded_requesting)

			hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

#endif

	}

	if (pipe_ctx->update_flags.bits.hubp_interdependent)

		hubp->funcs->hubp_setup_interdependent(
@@ -1597,6 +1608,12 @@ static void dcn20_program_pipe( 
			dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);

	}



#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)

		dc->res_pool->hubbub->funcs->program_det_size(

			dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

#endif



	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)

		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
@@ -1687,6 +1704,12 @@ void dcn20_program_front_end_for_ctx( 
	for (i = 0; i < dc->res_pool->pipe_count; i++)

		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable

				|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {

		#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

			struct hubbub *hubbub = dc->res_pool->hubbub;



			if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

				hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

		#endif

			hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);

			DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);

		}
@@ -1804,6 +1827,11 @@ void dcn20_prepare_bandwidth( 
					&context->bw_ctx.bw.dcn.watermarks,

					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,

					false);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	/* decrease compbuf size */

	if (hubbub->funcs->program_compbuf_size)

		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false);

#endif

}



void dcn20_optimize_bandwidth(
@@ -1822,6 +1850,11 @@ void dcn20_optimize_bandwidth( 
			dc->clk_mgr,

			context,

			true);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	/* increase compbuf size */

	if (hubbub->funcs->program_compbuf_size)

		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);

#endif

}



bool dcn20_update_bandwidth(
@@ -2539,6 +2572,10 @@ void dcn20_fpga_init_hw(struct dc *dc) 


		tg->funcs->tg_init(tg);

	}

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	if (dc->res_pool->hubbub->funcs->init_crb)

		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

#endif

}

#ifndef TRIM_FSFT

bool dcn20_optimize_timing_for_fsft(struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

+5 −0
Original line number Diff line number Diff line
@@ -651,6 +651,11 @@ void dcn30_init_hw(struct dc *dc) 
	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

		dc->res_pool->hubbub->funcs->force_pstate_change_control(

				dc->res_pool->hubbub, false, false);

#if defined(CONFIG_DRM_AMD_DC_DCN3_1)

	if (dc->res_pool->hubbub->funcs->init_crb)

		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);

#endif



}



void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)